MXPA01012805A - Substrato de capas multiples y metodo de fabricacion del mismo. - Google Patents
Substrato de capas multiples y metodo de fabricacion del mismo.Info
- Publication number
- MXPA01012805A MXPA01012805A MXPA01012805A MXPA01012805A MXPA01012805A MX PA01012805 A MXPA01012805 A MX PA01012805A MX PA01012805 A MXPA01012805 A MX PA01012805A MX PA01012805 A MXPA01012805 A MX PA01012805A MX PA01012805 A MXPA01012805 A MX PA01012805A
- Authority
- MX
- Mexico
- Prior art keywords
- resin film
- multilayer substrate
- sided conductor
- manufacturing
- laminate
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4638—Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
- H05K3/4617—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar single-sided circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4632—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating thermoplastic or uncured resin sheets comprising printed circuits without added adhesive materials between the sheets
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0104—Properties and characteristics in general
- H05K2201/0129—Thermoplastic polymer, e.g. auto-adhesive layer; Shaping of thermoplastic polymer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0388—Other aspects of conductors
- H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09245—Crossing layout
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/096—Vertically aligned vias, holes or stacked vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09854—Hole or via having special cross-section, e.g. elliptical
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/063—Lamination of preperforated insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/065—Binding insulating layers without adhesive, e.g. by local heating or welding, before lamination of the whole PCB
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
- H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/281—Applying non-metallic protective coatings by means of a preformed insulating foil
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/10—Methods of surface bonding and/or assembly therefor
- Y10T156/1052—Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing
- Y10T156/1062—Prior to assembly
- Y10T156/1064—Partial cutting [e.g., grooving or incising]
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
Proporcionar un metodo de manufactura de un sustrato de capas multiples que tenga electrodos en ambos lados de la misma que no sea complicado en el proceso de manufactura y que pueda ser de costo reducido. Extracto de la descripcion [medio para resolver el problema] Se laminan peliculas 21 con un patron conductor en un solo lado (que se muestran en (a) - (c)), cada una de las cuales tiene un patron 22 conductor formado unicamente en un lado de la pelicula 23 de resina y al cual se conduce un agujero de interconexion 24 y se rellena con la pasta 50 conductora, y una pelicula 31 con patron conductor en un solo lado la cual tiene un patron 22 conductor formado unicamente en un lado de una pelicula 23 de resina y en la cual se forma una abertura en la pelicula 23 de resina de manera que expone un electrodo 32, y ademas una capa de cubierta en la cual se forma una abertura para exponer un electrodo 37, se laminan en la superficie inferior de la misma. Despues, por 20 prensado mientras se calienta el laminado, se puede producir un sustrato 100 de capas multiples que tiene los electrodos en ambos lados del mismo.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000380634 | 2000-12-14 | ||
JP2001195375 | 2001-06-27 | ||
JP2001333021A JP3407737B2 (ja) | 2000-12-14 | 2001-10-30 | 多層基板の製造方法およびその製造方法によって形成される多層基板 |
Publications (1)
Publication Number | Publication Date |
---|---|
MXPA01012805A true MXPA01012805A (es) | 2004-08-12 |
Family
ID=27345444
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
MXPA01012805A MXPA01012805A (es) | 2000-12-14 | 2001-12-11 | Substrato de capas multiples y metodo de fabricacion del mismo. |
Country Status (8)
Country | Link |
---|---|
US (2) | US6667443B2 (es) |
EP (3) | EP2467004B1 (es) |
JP (1) | JP3407737B2 (es) |
KR (1) | KR100456121B1 (es) |
CN (1) | CN1199537C (es) |
MX (1) | MXPA01012805A (es) |
SG (1) | SG91948A1 (es) |
TW (1) | TW530006B (es) |
Families Citing this family (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6848912B2 (en) * | 2002-12-12 | 2005-02-01 | Broadcom Corporation | Via providing multiple electrically conductive paths through a circuit board |
JP3823981B2 (ja) * | 2003-05-12 | 2006-09-20 | セイコーエプソン株式会社 | パターンと配線パターン形成方法、デバイスとその製造方法、電気光学装置、電子機器及びアクティブマトリクス基板の製造方法 |
FI20031341A (fi) | 2003-09-18 | 2005-03-19 | Imbera Electronics Oy | Menetelmä elektroniikkamoduulin valmistamiseksi |
KR100659521B1 (ko) * | 2004-04-06 | 2006-12-20 | 가부시키가이샤 무라타 세이사쿠쇼 | 내부도체의 접속구조 및 다층기판 |
KR100546411B1 (ko) * | 2004-05-20 | 2006-01-26 | 삼성전자주식회사 | 플립 칩 패키지, 그 패키지를 포함하는 이미지 센서 모듈및 그 제조방법 |
FI117814B (fi) * | 2004-06-15 | 2007-02-28 | Imbera Electronics Oy | Menetelmä elektroniikkamoduulin valmistamiseksi |
JP2006081985A (ja) * | 2004-09-15 | 2006-03-30 | Seiko Epson Corp | パターン形成方法、電子機器の製造方法、および基体の製造方法 |
JP2006093438A (ja) * | 2004-09-24 | 2006-04-06 | Denso Corp | プリント基板及びその製造方法 |
US7227266B2 (en) * | 2004-11-09 | 2007-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure to reduce stress induced voiding effect |
JP4341588B2 (ja) * | 2005-06-09 | 2009-10-07 | 株式会社デンソー | 多層基板及びその製造方法 |
FI119714B (fi) | 2005-06-16 | 2009-02-13 | Imbera Electronics Oy | Piirilevyrakenne ja menetelmä piirilevyrakenteen valmistamiseksi |
FI122128B (fi) * | 2005-06-16 | 2011-08-31 | Imbera Electronics Oy | Menetelmä piirilevyrakenteen valmistamiseksi |
WO2006134220A1 (en) | 2005-06-16 | 2006-12-21 | Imbera Electronics Oy | Method for manufacturing a circuit board structure, and a circuit board structure |
JP4728708B2 (ja) * | 2005-06-17 | 2011-07-20 | 日本電気株式会社 | 配線基板及びその製造方法 |
JP5436774B2 (ja) | 2007-12-25 | 2014-03-05 | 古河電気工業株式会社 | 多層プリント基板およびその製造方法 |
JP4530089B2 (ja) * | 2008-03-12 | 2010-08-25 | 株式会社デンソー | 配線基板の製造方法 |
JP4548509B2 (ja) * | 2008-04-23 | 2010-09-22 | 株式会社デンソー | プリント基板製造装置 |
TW200950028A (en) * | 2008-05-20 | 2009-12-01 | Subtron Technology Co Ltd | Non-cylinder via structure and thermal enhanced substrate having the same |
JP2010056165A (ja) * | 2008-08-26 | 2010-03-11 | Denso Corp | 導体パターンフィルムの製造方法 |
JP5293060B2 (ja) * | 2008-10-02 | 2013-09-18 | 株式会社デンソー | 多層回路基板およびその製造方法 |
JP2010199318A (ja) * | 2009-02-25 | 2010-09-09 | Kyocera Corp | 配線基板及びそれを備えた実装構造体 |
CN101932196B (zh) * | 2009-06-25 | 2012-07-04 | 南亚电路板股份有限公司 | 电路板结构及其制造方法 |
JP2011066329A (ja) * | 2009-09-18 | 2011-03-31 | Tatsuta Electric Wire & Cable Co Ltd | シールドフィルム、そのシールドフィルムを有するシールド配線板、シールドフィルムにおけるグランド接続方法 |
US8488329B2 (en) * | 2010-05-10 | 2013-07-16 | International Business Machines Corporation | Power and ground vias for power distribution systems |
US8693203B2 (en) | 2011-01-14 | 2014-04-08 | Harris Corporation | Method of making an electronic device having a liquid crystal polymer solder mask laminated to an interconnect layer stack and related devices |
US8844125B2 (en) | 2011-01-14 | 2014-09-30 | Harris Corporation | Method of making an electronic device having a liquid crystal polymer solder mask and related devices |
JP5533914B2 (ja) * | 2011-08-31 | 2014-06-25 | 株式会社デンソー | 多層基板 |
JP2013074129A (ja) * | 2011-09-28 | 2013-04-22 | Kuraray Co Ltd | Lcp基板用カバー材およびそれを用いたlcp回路基板 |
WO2013141339A1 (ja) * | 2012-03-23 | 2013-09-26 | 株式会社村田製作所 | 多層配線基板およびその製造方法 |
US8877558B2 (en) | 2013-02-07 | 2014-11-04 | Harris Corporation | Method for making electronic device with liquid crystal polymer and related devices |
US9293438B2 (en) | 2013-07-03 | 2016-03-22 | Harris Corporation | Method for making electronic device with cover layer with openings and related devices |
JP5874697B2 (ja) | 2013-08-28 | 2016-03-02 | 株式会社デンソー | 多層プリント基板およびその製造方法 |
US9801275B2 (en) | 2014-02-17 | 2017-10-24 | Lg Innotek Co., Ltd. | Printed circuit board and method of manufacturing the same |
JP6626258B2 (ja) * | 2014-04-07 | 2019-12-25 | 昭和電工パッケージング株式会社 | ラミネート外装材の製造方法 |
CN206908962U (zh) | 2014-09-04 | 2018-01-19 | 株式会社村田制作所 | 部件内置基板 |
JP6380547B2 (ja) * | 2014-09-30 | 2018-08-29 | 株式会社村田製作所 | 多層基板 |
JP6372624B2 (ja) * | 2016-05-18 | 2018-08-15 | 株式会社村田製作所 | 多層基板、および、多層基板の製造方法 |
JP6623941B2 (ja) | 2016-06-09 | 2019-12-25 | 株式会社デンソー | 多層基板の製造方法 |
JP2018156990A (ja) * | 2017-03-15 | 2018-10-04 | 株式会社東芝 | モジュール、電子機器、及び配線板 |
WO2019082714A1 (ja) | 2017-10-26 | 2019-05-02 | 株式会社村田製作所 | 多層基板、インターポーザおよび電子機器 |
CN216531888U (zh) | 2019-02-05 | 2022-05-13 | 株式会社村田制作所 | 树脂多层基板 |
WO2021025025A1 (ja) * | 2019-08-08 | 2021-02-11 | 株式会社村田製作所 | 樹脂多層基板および樹脂多層基板の製造方法 |
US11699688B2 (en) | 2019-12-03 | 2023-07-11 | Nichia Corporation | Surface-emitting light source and method of manufacturing the same |
CN113939115B (zh) * | 2021-12-15 | 2022-05-27 | 深圳市信维通信股份有限公司 | 一种多层lcp基板的加工方法 |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2736677A (en) * | 1950-12-01 | 1956-02-28 | Technograph Printed Circuits L | Metallized insulators |
GB1430640A (en) * | 1973-05-15 | 1976-03-31 | Minnesota Mining & Mfg | Printed circuits and their manufacture |
JPS60137092A (ja) * | 1983-12-19 | 1985-07-20 | 株式会社東芝 | 回路基板の製造方法 |
US4915983A (en) * | 1985-06-10 | 1990-04-10 | The Foxboro Company | Multilayer circuit board fabrication process |
US4763403A (en) * | 1986-12-16 | 1988-08-16 | Eastman Kodak Company | Method of making an electronic component |
GB8705543D0 (en) * | 1987-03-10 | 1987-04-15 | Int Computers Ltd | Printed circuit board |
JP3059568B2 (ja) | 1992-01-23 | 2000-07-04 | 古河電気工業株式会社 | 多層プリント回路基板の製造方法 |
EP0647090B1 (en) * | 1993-09-03 | 1999-06-23 | Kabushiki Kaisha Toshiba | Printed wiring board and a method of manufacturing such printed wiring boards |
JP3087152B2 (ja) * | 1993-09-08 | 2000-09-11 | 富士通株式会社 | 樹脂フィルム多層回路基板の製造方法 |
JPH07263867A (ja) | 1994-03-18 | 1995-10-13 | Fujitsu General Ltd | 多層配線基板 |
JPH09199635A (ja) | 1996-01-19 | 1997-07-31 | Shinko Electric Ind Co Ltd | 回路基板形成用多層フィルム並びにこれを用いた多層回路基板および半導体装置用パッケージ |
JP3944921B2 (ja) | 1996-04-05 | 2007-07-18 | 日立化成工業株式会社 | 多層配線板の製造方法 |
DE19681758B4 (de) * | 1996-06-14 | 2006-09-14 | Ibiden Co., Ltd. | Einseitiges Schaltkreissubstrat für mehrlagige Schaltkreisplatine, mehrlagige Schaltkreisplatine und Verfahren zur Herstellung selbiger |
JP3513827B2 (ja) * | 1996-07-01 | 2004-03-31 | 日立化成工業株式会社 | 多層プリント配線板用塑性流動シート及びそれを用いた多層プリント配線板の製造方法 |
US6237218B1 (en) * | 1997-01-29 | 2001-05-29 | Kabushiki Kaisha Toshiba | Method and apparatus for manufacturing multilayered wiring board and multi-layered wiring board |
WO1998056220A1 (fr) * | 1997-06-06 | 1998-12-10 | Ibiden Co., Ltd. | Plaquette de circuit simple face et procede de fabrication de ladite plaquette |
JPH10341082A (ja) | 1997-06-10 | 1998-12-22 | Kyocera Corp | 多層配線基板 |
US6159586A (en) * | 1997-09-25 | 2000-12-12 | Nitto Denko Corporation | Multilayer wiring substrate and method for producing the same |
JP3355142B2 (ja) * | 1998-01-21 | 2002-12-09 | 三菱樹脂株式会社 | 耐熱性積層体用フィルムとこれを用いたプリント配線基板用素板および基板の製造方法 |
JP4043115B2 (ja) | 1998-09-24 | 2008-02-06 | イビデン株式会社 | 多数個取り多層プリント配線板 |
JP3514647B2 (ja) | 1999-01-05 | 2004-03-31 | 三菱樹脂株式会社 | 多層プリント配線板およびその製造方法 |
JP2000323839A (ja) | 1999-03-04 | 2000-11-24 | Soshin Electric Co Ltd | 多層基板の製造方法 |
JP2000277924A (ja) | 1999-03-23 | 2000-10-06 | Hitachi Chem Co Ltd | 多層プリント配線板とその製造方法 |
-
2001
- 2001-10-30 JP JP2001333021A patent/JP3407737B2/ja not_active Expired - Fee Related
- 2001-12-10 US US10/007,703 patent/US6667443B2/en not_active Expired - Lifetime
- 2001-12-11 MX MXPA01012805A patent/MXPA01012805A/es active IP Right Grant
- 2001-12-12 TW TW090130808A patent/TW530006B/zh not_active IP Right Cessation
- 2001-12-13 EP EP12159297.6A patent/EP2467004B1/en not_active Expired - Lifetime
- 2001-12-13 EP EP01129757A patent/EP1215948B1/en not_active Expired - Lifetime
- 2001-12-13 SG SG200107803A patent/SG91948A1/en unknown
- 2001-12-13 KR KR10-2001-0078966A patent/KR100456121B1/ko not_active IP Right Cessation
- 2001-12-13 EP EP09005588A patent/EP2079292A3/en not_active Ceased
- 2001-12-14 CN CNB011438223A patent/CN1199537C/zh not_active Expired - Fee Related
-
2003
- 2003-06-11 US US10/458,630 patent/US6855625B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
CN1199537C (zh) | 2005-04-27 |
EP2467004A2 (en) | 2012-06-20 |
SG91948A1 (en) | 2002-10-15 |
US6667443B2 (en) | 2003-12-23 |
CN1360464A (zh) | 2002-07-24 |
US6855625B2 (en) | 2005-02-15 |
EP2079292A2 (en) | 2009-07-15 |
US20020076903A1 (en) | 2002-06-20 |
KR20020048293A (ko) | 2002-06-22 |
EP1215948B1 (en) | 2011-05-25 |
EP2467004A3 (en) | 2013-07-17 |
EP2467004B1 (en) | 2014-04-30 |
TW530006B (en) | 2003-05-01 |
JP3407737B2 (ja) | 2003-05-19 |
JP2003086948A (ja) | 2003-03-20 |
US20030209796A1 (en) | 2003-11-13 |
EP2079292A3 (en) | 2009-10-28 |
EP1215948A2 (en) | 2002-06-19 |
EP1215948A3 (en) | 2004-07-21 |
KR100456121B1 (ko) | 2004-11-08 |
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