KR970077719A - 둘 이상의 본딩 옵션 패드를 갖는 반도체 장치 - Google Patents

둘 이상의 본딩 옵션 패드를 갖는 반도체 장치 Download PDF

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KR970077719A
KR970077719A KR1019970018931A KR19970018931A KR970077719A KR 970077719 A KR970077719 A KR 970077719A KR 1019970018931 A KR1019970018931 A KR 1019970018931A KR 19970018931 A KR19970018931 A KR 19970018931A KR 970077719 A KR970077719 A KR 970077719A
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semiconductor device
bonding option
pad
signal
bonding
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KR1019970018931A
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KR100291130B1 (ko
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카츠토시 이와타
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가네꼬 히사시
닛폰 덴키 가부시키가이샤
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Dram (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

둘 이상의 본딩 옵션 패드가 반도체 칩상에 소정의 방향으로 정렬된다. 높고 낮은 전위 측면상의 도선들은 그 도선들이 소정의 방향을 가로지르는 방향으로 확장하도록 본딩 옵션 패드의 양측면상에 제공된다. 최소한의 한 본딩 옵션 패드는 본딩 와이어에 의해 상기 도선들 중 최소한의 하나에 접속된다.

Description

둘 이상의 본딩 옵션 패드를 갖는 반도체 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명의 제1실시예에 따른 반도체 장치를 설명하는데 이용할 평면도.

Claims (10)

  1. 반도체 칩상에 소정의 방향으로 배열된 둘 이상의 본딩 옵션 패드와 상기 반도체 칩상에 배열된 고전위 및 저전위 측면상의, 상기 본딩 옵션 패드의 양측상에 위치 도선을 포함하는 반도체 장치에 있어서, 상기 고전위 및 저전위 측면상의 상기 도선은 각각 상기 소정의 방향을 가로질러 서로 떨어져있는 소정의 방향으로 확장하는 일부분을 갖는것을 특징으로 하는 반도체 장치.
  2. 제1항에 있어서, 상기 도선중 최소한의 하나는 상기 본딩 옵션 패드중 하나에 접속되는 것을 특징으로 하는 반도체 장치.
  3. 제1항에 있어서, 상기 도선중 최소한의 하나는 상기 본딩 옵션 패드에 인접하는 위치에서 분기되거나 또는 갈라지는 것을 특징으로 하는 반도체 장치.
  4. 제1항에 있어서, 상기 각각의 도선은 상기 소정의 방향으로 확장하는 상기 일부분을 갖는 것을 특징으로 하는 반도체 장치.
  5. 제1항에 있어서, 상기 본딩 옵션 패드는 단일 패드를 포함하며, 상기 신호 도선은 상기 반도체 칩상에 제공되며, 상기 신호 도선은 상기 도선에 인접하는 것과 함께 상기 신호 패드에 접속되며, 상기 신호 도선은 상기 도선을 가로지르지 않고 상기 신호 도선 및 상기 신호 패드 사이의 접속을 허용하도록 배열되는 것을 특징으로 하는 반도체 장치.
  6. 제1항에 있어서, 상기 반도체 칩은 칩상 도선(lead-on-chip) 구조 또는 선상 칩(chip-on-lead) 구조를 갖는 것을 특징으로 하는 반도체 장치.
  7. 제1항에 있어서, 상기 본딩 옵션 패드는 상기 반도체 칩의 중앙 부분에 배열되는 것을 특징으로 하는 반도체 장치.
  8. 제1항에 있어서, 상기 본딩 옵션 패드로부터 공급된 신호를 디코딩하기 위한 디코더를 더 포함하며, 상기 디코더는 상기 본딩 옵션 패드 및 상기 도선에 접속되며, 상기 반도체 장치의 동작 모드는 상기 디코더에 의해 선택되는 것을 특징으로 하는 반도체 장치.
  9. 제1항 내지 제3항 중 어느 한 항에 있어서, 상기 도선들은 둘 이상의 본딩 포인트에서 상기 본딩 옵션 패드에 접속되는 것을 특징으로 하는 반도체 장치.
  10. 제1항에 있어서, 상기 도선들 중 최소한의 하나는 둘 이상의 위치에서 상기 본딩 옵션 패드와의 접속을 허용하는 구조를 갖는 것을 특징으로 하는 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
KR1019970018931A 1996-05-16 1997-05-16 둘이상의본딩옵션패드를갖는반도체장치 KR100291130B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP8121240A JP2795315B2 (ja) 1996-05-16 1996-05-16 半導体装置
JP96-121240 1996-05-16

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KR970077719A true KR970077719A (ko) 1997-12-12
KR100291130B1 KR100291130B1 (ko) 2001-09-17

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JP2000100814A (ja) * 1998-09-18 2000-04-07 Hitachi Ltd 半導体装置
JP2001053243A (ja) * 1999-08-06 2001-02-23 Hitachi Ltd 半導体記憶装置とメモリモジュール
JP4022040B2 (ja) * 2000-10-05 2007-12-12 松下電器産業株式会社 半導体デバイス
JP2002299568A (ja) * 2001-04-02 2002-10-11 Fujitsu Ltd Ｉｃチップ
US6525560B1 (en) 2001-12-12 2003-02-25 Xilinx, Inc. Method and structure for shipping a die as multiple products
US7131033B1 (en) 2002-06-21 2006-10-31 Cypress Semiconductor Corp. Substrate configurable JTAG ID scheme
JP2004055080A (ja) * 2002-07-23 2004-02-19 Renesas Technology Corp 半導体メモリモジュールおよびそれに用いる半導体チップの製造方法
US7818640B1 (en) 2004-10-22 2010-10-19 Cypress Semiconductor Corporation Test system having a master/slave JTAG controller
US7923829B2 (en) * 2008-05-06 2011-04-12 Mediatek Inc. Bonding pad sharing method applied to multi-chip module and apparatus thereof
WO2016176692A2 (en) * 2016-06-17 2016-11-03 Ohmx Corporation Biosensor chip

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EP0454447A3 (en) * 1990-04-26 1993-12-08 Hitachi Ltd Semiconductor device assembly
JP2890269B2 (ja) * 1991-02-22 1999-05-10 株式会社日立製作所 半導体装置
US5280605A (en) * 1991-05-03 1994-01-18 Intel Corporation Clock speed limiter for microprocessor
JPH0562465A (ja) * 1991-08-30 1993-03-12 Hitachi Ltd ボンデイングオプシヨン回路、及び半導体集積回路
US5563443A (en) * 1993-03-13 1996-10-08 Texas Instruments Incorporated Packaged semiconductor device utilizing leadframe attached on a semiconductor chip
JPH0737931A (ja) * 1993-07-16 1995-02-07 Hitachi Ltd テープキャリア型半導体装置
JPH07130788A (ja) * 1993-09-09 1995-05-19 Mitsubishi Electric Corp 半導体集積回路装置

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US5982043A (en) 1999-11-09
KR100291130B1 (ko) 2001-09-17
JP2795315B2 (ja) 1998-09-10

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