KR970072099A - 반도체 소자 제조를 위한 포토마스크 및 그 형성방법 - Google Patents

반도체 소자 제조를 위한 포토마스크 및 그 형성방법 Download PDF

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Publication number
KR970072099A
KR970072099A KR1019960013191A KR19960013191A KR970072099A KR 970072099 A KR970072099 A KR 970072099A KR 1019960013191 A KR1019960013191 A KR 1019960013191A KR 19960013191 A KR19960013191 A KR 19960013191A KR 970072099 A KR970072099 A KR 970072099A
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South Korea
Prior art keywords
metal pattern
metal
designing
semiconductor device
forming
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KR1019960013191A
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English (en)
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KR100190365B1 (ko
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허연철
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김주용
현대전자산업 주식회사
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Priority to KR1019960013191A priority Critical patent/KR100190365B1/ko
Priority to TW086104107A priority patent/TW358986B/zh
Priority to US08/832,349 priority patent/US5926733A/en
Priority to CN97109704A priority patent/CN1099696C/zh
Priority to JP11160397A priority patent/JPH1056015A/ja
Publication of KR970072099A publication Critical patent/KR970072099A/ko
Application granted granted Critical
Publication of KR100190365B1 publication Critical patent/KR100190365B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/928—Front and rear surface processing

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Drying Of Semiconductors (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)

Abstract

본 발명은 통상적인 종래 기술로 제1금속패턴을 설계하는 단계; 상기 제1금속패터의 각 방향으로 소정 거리 오버사이징한 다음, 오버사이징된 제1금속패턴의 음양이 반전된 제2금속패턴을 설계하는 단계; 및 상기 제1금속패턴과 상기 제2금속패턴을 합성하여 소자에 적용되는 금속 배선을 설계하는 것을 특징으로 하는 반도체 소자의 금속배선 설계방법 및 소자의 전지역에 걸쳐 각 금속패턴간의 스페이싱이 균일하게 형성된 것을 특징으로 하는 금속배선에 관한 것으로, 소자 각 지역의 금속패턴간의 스페이싱을 일정하게 설계함으로써, 과도식각에 의한 소자의 열화를 방지할 뿐만 아니라, 금속배선 공정시 금속배선에서 유기되는 전류를 줄여 주기 때문에 전류억제를 위한 별도의 접합이나 콘택을 형성해야 하는 등의 복잡한 과정을 거치지 않아도 된다.

Description

반도체 소자 제조를 위한 포토마스크 및 그 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2A도 내지 제2D도는 본 발명의 일실시예에 따른 반도체 소자의 금속배선 설계도이다.

Claims (4)

  1. 반도체 소자 설계방법에 있어서, 통상적인 종래 기술로 제1금속패턴을 설계하는 단계; 상기 제1금속패턴의 각 방향으로 소정 거리 오버사이징(Oversizing)한 다음, 오버사이징된 제1금속패턴의 음양이 반전된 제2금속패턴을 설계하는 단계; 및 상기 제1금속패턴과 상기 제2금속패턴을 합성하여 소자에 적용되는 금속배선을 설계하는 것을 특징으로 하는 반도체 소자의 금속 배선 설계방법.
  2. 제1항에 있어서, 상기 오버사이징한 거리는 0.2㎛ 내지 1.0㎛인 것을 특징으로 하는 반도체 소자의 금속 배선 설계방법.
  3. 반도체 소자 설계방법에 있어서, 통상적인 종래 기술로 제1금속패턴을 설계하는 단계; 상기 제1금속패턴의 음양을 반전한 다음, 반전된 제1금속패턴의 각 방향으로 소정 거리 언더사이징(Undersizing)하여, 제2금속패턴을 설계하는 단계; 및 상기 제1금속패턴과 상기 제2금속패턴을 합성하여 소자에 적용되는 금속배선을 설계하는 것을 특징으로 하는 반도체 소자의 금속 배선 설계방법.
  4. 제3항에 있어서, 상기 언더사이징한 거리는 0.2㎛ 내지 1.0㎛인 것을 특징으로 하는 반도체 소자의 금속 배선 설계방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960013191A 1996-04-26 1996-04-26 반도체 소자 제조를 위한 포토마스크 및 그 형성 방법 KR100190365B1 (ko)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1019960013191A KR100190365B1 (ko) 1996-04-26 1996-04-26 반도체 소자 제조를 위한 포토마스크 및 그 형성 방법
TW086104107A TW358986B (en) 1996-04-26 1997-03-31 Metal layer patterns of a semiconductor device and a method for forming the same
US08/832,349 US5926733A (en) 1996-04-26 1997-04-02 Metal layer patterns of a semiconductor device and a method for forming the same
CN97109704A CN1099696C (zh) 1996-04-26 1997-04-26 半导体器件的金属层图案和形成这种金属层图案的方法
JP11160397A JPH1056015A (ja) 1996-04-26 1997-04-28 半導体装置および半導体素子の金属配線形成用ホトマスクとその形成方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960013191A KR100190365B1 (ko) 1996-04-26 1996-04-26 반도체 소자 제조를 위한 포토마스크 및 그 형성 방법

Publications (2)

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KR970072099A true KR970072099A (ko) 1997-11-07
KR100190365B1 KR100190365B1 (ko) 1999-06-01

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US (1) US5926733A (ko)
JP (1) JPH1056015A (ko)
KR (1) KR100190365B1 (ko)
CN (1) CN1099696C (ko)
TW (1) TW358986B (ko)

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* Cited by examiner, † Cited by third party
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US7001713B2 (en) * 1998-04-18 2006-02-21 United Microelectronics, Corp. Method of forming partial reverse active mask
TW392292B (en) * 1998-08-11 2000-06-01 United Microelectronics Corp Method for improving trench polishing
JP2001168098A (ja) * 1999-12-10 2001-06-22 Seiko Epson Corp 半導体装置及びパターンデータ作成方法
US6777813B2 (en) * 2001-10-24 2004-08-17 Micron Technology, Inc. Fill pattern generation for spin-on-glass and related self-planarization deposition
US6815787B1 (en) * 2002-01-08 2004-11-09 Taiwan Semiconductor Manufacturing Company Grid metal design for large density CMOS image sensor
JP2004354605A (ja) * 2003-05-28 2004-12-16 Matsushita Electric Ind Co Ltd 半導体設計レイアウトパタン生成方法および図形パタン生成装置
US7235424B2 (en) * 2005-07-14 2007-06-26 Taiwan Semiconductor Manufacturing Co., Ltd. Method and apparatus for enhanced CMP planarization using surrounded dummy design
CN101341595A (zh) * 2005-12-14 2009-01-07 飞思卡尔半导体公司 形成具有伪特征的半导体器件的方法
US7765235B2 (en) * 2005-12-29 2010-07-27 Rovi Guides, Inc. Systems and methods for resolving conflicts and managing system resources in multimedia delivery systems
US7934173B2 (en) * 2008-01-14 2011-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Reverse dummy insertion algorithm
CN103170906B (zh) * 2013-03-14 2016-08-10 上海华力微电子有限公司 检测研磨工艺负载效应的方法

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JPH01295443A (ja) * 1987-12-28 1989-11-29 Mitsubishi Electric Corp 微細パターン形成方法
DE3902693C2 (de) * 1988-01-30 1995-11-30 Toshiba Kawasaki Kk Mehrebenenverdrahtung für eine integrierte Halbleiterschaltungsanordnung und Verfahren zur Herstellung von Mehrebenenverdrahtungen für integrierte Halbleiterschaltungsanordnungen
JP2695821B2 (ja) * 1988-03-22 1998-01-14 株式会社東芝 半導体集積回路装置
JPH04307958A (ja) * 1991-04-05 1992-10-30 Hitachi Ltd 半導体集積回路装置の製造方法
KR930008894B1 (ko) * 1991-09-19 1993-09-16 삼성전자 주식회사 반도체장치의 금속배선구조
JPH06216249A (ja) * 1993-01-13 1994-08-05 Nec Ic Microcomput Syst Ltd Ｉｃチップ自動レイアウト設計システム
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Also Published As

Publication number Publication date
CN1166050A (zh) 1997-11-26
CN1099696C (zh) 2003-01-22
US5926733A (en) 1999-07-20
JPH1056015A (ja) 1998-02-24
TW358986B (en) 1999-05-21
KR100190365B1 (ko) 1999-06-01

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