TW358986B - Metal layer patterns of a semiconductor device and a method for forming the same - Google Patents

Metal layer patterns of a semiconductor device and a method for forming the same

Info

Publication number
TW358986B
TW358986B TW086104107A TW86104107A TW358986B TW 358986 B TW358986 B TW 358986B TW 086104107 A TW086104107 A TW 086104107A TW 86104107 A TW86104107 A TW 86104107A TW 358986 B TW358986 B TW 358986B
Authority
TW
Taiwan
Prior art keywords
semiconductor device
forming
same
metal layer
layer patterns
Prior art date
Application number
TW086104107A
Other languages
English (en)
Inventor
Yeon-Cheol Heo
Original Assignee
Hyundai Electronics Ind
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Ind filed Critical Hyundai Electronics Ind
Application granted granted Critical
Publication of TW358986B publication Critical patent/TW358986B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/928Front and rear surface processing

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Drying Of Semiconductors (AREA)
TW086104107A 1996-04-26 1997-03-31 Metal layer patterns of a semiconductor device and a method for forming the same TW358986B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960013191A KR100190365B1 (ko) 1996-04-26 1996-04-26 반도체 소자 제조를 위한 포토마스크 및 그 형성 방법

Publications (1)

Publication Number Publication Date
TW358986B true TW358986B (en) 1999-05-21

Family

ID=19456895

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086104107A TW358986B (en) 1996-04-26 1997-03-31 Metal layer patterns of a semiconductor device and a method for forming the same

Country Status (5)

Country Link
US (1) US5926733A (zh)
JP (1) JPH1056015A (zh)
KR (1) KR100190365B1 (zh)
CN (1) CN1099696C (zh)
TW (1) TW358986B (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7001713B2 (en) * 1998-04-18 2006-02-21 United Microelectronics, Corp. Method of forming partial reverse active mask
TW392292B (en) * 1998-08-11 2000-06-01 United Microelectronics Corp Method for improving trench polishing
JP2001168098A (ja) * 1999-12-10 2001-06-22 Seiko Epson Corp 半導体装置及びパターンデータ作成方法
US6777813B2 (en) * 2001-10-24 2004-08-17 Micron Technology, Inc. Fill pattern generation for spin-on-glass and related self-planarization deposition
US6815787B1 (en) * 2002-01-08 2004-11-09 Taiwan Semiconductor Manufacturing Company Grid metal design for large density CMOS image sensor
JP2004354605A (ja) * 2003-05-28 2004-12-16 Matsushita Electric Ind Co Ltd 半導体設計レイアウトパタン生成方法および図形パタン生成装置
US7235424B2 (en) * 2005-07-14 2007-06-26 Taiwan Semiconductor Manufacturing Co., Ltd. Method and apparatus for enhanced CMP planarization using surrounded dummy design
CN101341595A (zh) * 2005-12-14 2009-01-07 飞思卡尔半导体公司 形成具有伪特征的半导体器件的方法
US7765235B2 (en) * 2005-12-29 2010-07-27 Rovi Guides, Inc. Systems and methods for resolving conflicts and managing system resources in multimedia delivery systems
US7934173B2 (en) * 2008-01-14 2011-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Reverse dummy insertion algorithm
CN103170906B (zh) * 2013-03-14 2016-08-10 上海华力微电子有限公司 检测研磨工艺负载效应的方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01295443A (ja) * 1987-12-28 1989-11-29 Mitsubishi Electric Corp 微細パターン形成方法
DE3902693C2 (de) * 1988-01-30 1995-11-30 Toshiba Kawasaki Kk Mehrebenenverdrahtung für eine integrierte Halbleiterschaltungsanordnung und Verfahren zur Herstellung von Mehrebenenverdrahtungen für integrierte Halbleiterschaltungsanordnungen
JP2695821B2 (ja) * 1988-03-22 1998-01-14 株式会社東芝 半導体集積回路装置
JPH04307958A (ja) * 1991-04-05 1992-10-30 Hitachi Ltd 半導体集積回路装置の製造方法
KR930008894B1 (ko) * 1991-09-19 1993-09-16 삼성전자 주식회사 반도체장치의 금속배선구조
JPH06216249A (ja) * 1993-01-13 1994-08-05 Nec Ic Microcomput Syst Ltd Icチップ自動レイアウト設計システム
US5494853A (en) * 1994-07-25 1996-02-27 United Microelectronics Corporation Method to solve holes in passivation by metal layout

Also Published As

Publication number Publication date
US5926733A (en) 1999-07-20
CN1166050A (zh) 1997-11-26
KR970072099A (ko) 1997-11-07
JPH1056015A (ja) 1998-02-24
CN1099696C (zh) 2003-01-22
KR100190365B1 (ko) 1999-06-01

Similar Documents

Publication Publication Date Title
TW373256B (en) A semiconductor device having discontinuous insulating regions and the manufacturing method thereof
EP1120818A4 (en) SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING SAME, SEMICONDUCTOR DEVICE COMPRISING SUCH A SUBSTRATE, AND METHOD FOR MANUFACTURING THE SAME
GB9503419D0 (en) Semiconductor device,production method therefor,method for testing semiconductor elements,test substrate for the method and method for producing the test
EP0951057A4 (en) SUBSTRATE SMOOTHING METHOD AND FILM-COATED SUBSTRATE AND METHOD FOR PRODUCING A SEMICONDUCTOR ARRANGEMENT
EP0771029A3 (en) Semiconductor device with improved structure to avoid cracks and manufacturing process
TW358992B (en) Semiconductor device and method of fabricating the same
TW337035B (en) Semiconductor device and method of manufacturing the same
TW336347B (en) Semiconductor device, method of manufacturing the same
GB2316226B (en) Epitaxial wafer for light-emitting device,method of forming the wafer and light-emitting device using the wafer
TW339473B (en) Electronic package with multilevel connections
SG63669A1 (en) Semiconductor substrate and producing method thereof
EP0723303A3 (en) Semiconductor light-emitting device and manufacturing method
EP0713250A3 (en) Material for semiconductor substrate, its manufacture and product from this substrate
AU2854099A (en) Semiconductor device and method for manufacturing the same, circuit substrate, and electronic device
TW358986B (en) Metal layer patterns of a semiconductor device and a method for forming the same
EP0666336A4 (en) HIGH MELTING POINT METAL SILICIDE TARGET, MANUFACTURING METHOD THEREOF, HIGH MELTING POINT METAL SILICIDE LAYER, AND SEMICONDUCTOR DEVICE.
TW337590B (en) Manufacture of semiconductor device having reliable and fine connection hole
EP0619602A3 (en) Semiconductor device and manufacturing method.
MY118901A (en) Method for manufacturing a photoresist pattern defining a small opening and method for manufacturing semiconductor device using the same
EP0607820A3 (en) Method for manufacturing a semiconductor device comprising a layer of metallic silicide on a diffused region.
TW356586B (en) Semiconductor device having conductive layer and manufacturing method thereof
TW370693B (en) Method for forming a contact to a substrate
TW337610B (en) Structure with reduced stress between a spin-on-glass layer and a metal layer and process for producing the same
TW357469B (en) Semiconductor laser and the manufacturing method thereof
TW350973B (en) Semiconductor and semiconductor layout

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees