KR970053413A - 반도체소자의 소자분리막 제조방법 - Google Patents

반도체소자의 소자분리막 제조방법 Download PDF

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KR970053413A
KR970053413A KR1019950054961A KR19950054961A KR970053413A KR 970053413 A KR970053413 A KR 970053413A KR 1019950054961 A KR1019950054961 A KR 1019950054961A KR 19950054961 A KR19950054961 A KR 19950054961A KR 970053413 A KR970053413 A KR 970053413A
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pattern
oxide film
film
semiconductor substrate
oxide
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KR1019950054961A
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KR100364124B1 (ko
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김영복
이길호
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김주용
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02592—Microstructure amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

본 발명은 반도체소자의 소자분리막 제조방법에 관한 것으로, 본 발명은 LOCOS(Local Oxidation of Silicon) 공정을 이용한 소자분리막 제조방법에서, 반도체기판의 상부에 패드산화막패턴과, 질화막패턴, 폴리실리콘패턴을 차례로 형성하고, 상기 폴리실리콘패턴을 산화하여 부피 팽창하고, 상기 산화된 폴리실리콘패턴을 마스크로 반도체기판을 식각한 후, 필드산화막을 형성하므로써, 필드산화막의 충분한 두께를 확보할 수 있으며, 반도체기판과 질화막과의 접촉이 없으므로 전기적인 특성을 향상할 수 있으며, 필드산화막의 평탄화 특성이 우수하다.

Description

반도체소자의 소자분리막 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2A도 내지 제2G도는 본 발명의 실시예에 따른 반도체소자의 소자분리막 제조 공정도.

Claims (8)

  1. 반도체기판의 상부에 패드산화막과, 질화막, 폴리실리콘층을 차례로 형성하는 단계와, 소자분리용 마스크를 이용하여 폴리실리콘패턴, 질화막패턴, 및 패드산화막패턴을 형성하는 단계와, 폴리실리콘패턴을 열산화하여 제1산화막을 형성하는 동시에 노출된 반도체기판을 열산화하여 제2산화막을 형성하는 단계와, 상기 제1산화막을 마스크로 상기 제2산호막을 건식식각하므로써, 제2산화막패턴을 형성하는 단계와, 상기 제2산화막패턴을 마스크로 반도체기판을 식각하여 홈을 형성하는 단계와, 상기 제2산화막패턴을 제거하는 단계와, 상기 홈이 형성된 부위의 반도체기판을 산화하여 필드산화막을 형성하는 단계와, 상기 절화막패턴과, 패드산화막패턴을 제거하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 소자분리막 제조방법.
  2. 제1항에 있어서, 상기 패드산화막은 600 내지 1000℃에서 열산화하여 30 내지 300Å 두께로 형성하는 것을 특징으로 하는 반도체소자의 소자분리막 제조방법.
  3. 제1항에 있어서, 상기 질화막은 700 내지 3000Å 두께로 형성하는 것을 특징으로 하는 반도체소자의 소자분리막 제조방법.
  4. 제1항에 있어서, 상기 폴리실리콘층은 200 내지 700Å 두께로 형성하는 것을 특징으로 하는 반도체소자의 소자분리막 제조방법.
  5. 제1항에 있어서, 상기 폴리실리콘층 대신에 상기 폴리실리콘층과 같은 두께의 비정질폴리실리콘층을 형성하는 것을 특징으로 하는 반도체소자의 소자분리막 제조방법.
  6. 제1항에 있어서, 상기 제1산화막패턴은, 제2산화막패턴은 600 내지 1000℃에서 형성하는 것을 특징으로 하는 반도체소자의 소자분리막 제조방법.
  7. 제1항에 있어서, 상기 홈을 형성할 때, 반도체기판을 200 내지 700Å 식각하는 것을 특징으로 하는 반도체소자의 소자분리막 제조방법.
  8. 제1항에 있어서, 상기 필드산화막은 700 내지 1200℃의 온도에서 1000~5000Å 두께로 형성하는 것을 특징으로 하는 반도체소자의 소자분리막 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950054961A 1995-12-22 1995-12-22 반도체소자의소자분리막제조방법 KR100364124B1 (ko)

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KR1019950054961A KR100364124B1 (ko) 1995-12-22 1995-12-22 반도체소자의소자분리막제조방법

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KR1019950054961A KR100364124B1 (ko) 1995-12-22 1995-12-22 반도체소자의소자분리막제조방법

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62136026A (ja) * 1985-12-09 1987-06-19 Nec Corp 半導体装置の製造方法
JPS63234547A (ja) * 1987-03-24 1988-09-29 Oki Electric Ind Co Ltd 半導体素子の製造方法
KR880013236A (ko) * 1987-04-30 1988-11-30 강진구 반도체 장치의 제조방법
KR910007105A (ko) * 1989-09-09 1991-04-30 정몽현 폴리 실리콘을 이용한 소자분리 산화막 제조방법
JPH05304143A (ja) * 1992-04-28 1993-11-16 Sharp Corp 素子分離領域の形成方法

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