KR970023759A - 반도체장치 및 그 제조방법 - Google Patents
반도체장치 및 그 제조방법 Download PDFInfo
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- KR970023759A KR970023759A KR1019960030596A KR19960030596A KR970023759A KR 970023759 A KR970023759 A KR 970023759A KR 1019960030596 A KR1019960030596 A KR 1019960030596A KR 19960030596 A KR19960030596 A KR 19960030596A KR 970023759 A KR970023759 A KR 970023759A
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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Abstract
막 수축이 감소하고. 막 스트레스가 저감되도록 개량된 층간절연막을 갖는 반도체 장치를 제공하기 위해, 기판(1)상에 금속배선(2a, 2b)가 형성되어 있다. 금속배선(2a, 2b)를 덮도록, 또한 금속배선(2a)와 금속배선(2b) 사이의 틈을 매립하도록, 기판(1)상에 실리콘산화막(4)이 마련되어 있다. 실리콘산화막(4)의 화학구조식은 Si-F결합을 포함하고 있다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
도1-3은 본 발명의 실시예 1에 관한 반도체장치의 제조방법의 순서의 제1-3의 공정 각각에 있어서의 반도체장치의 단면도.
Claims (12)
- 기판(1), 상기 기판(1)상에 형성된 제1의 금속배선(2a)과 제2의 금속배선(2b), 상기 기판(1)상에 형성되어 상기 제1 및 제2의 금속배선(2a, 2b)을 덮고, 또한 상기 제1의 금속배선(2a)와 상기 제2의 금속배선(2b)의 틈 사이를 매립하는, 실리콘산화막(4)을 포함하고, 상기 실리콘산화막(4)의 화학구조식은 Si-F결합을 포함하는 반도체장치.
- 제1항에 있어서, 상기 실리콘산화막(4)의 화학구조식은 산소원자로 서로 연결된 제1의 실리콘원자와 제2의 실리콘원자를 갖는 단위를 갖고, 상기 제1의 실리콘원자에는 또, 2개의 산소원자가 결합되어 있고, 상기 제2의 실리콘 원자에는 1∼3개의 불소원자가 결합되어 있는 반도체장치.
- 제1항에 있어서, 상기 제1 및 제2의 금속배선(2a, 2b)상에 놓여있는 상기 실리콘산화막(4)의 두께를 a라 하고, 상기 기판(1)상에 놓여있고 또한 상기 제1의 금속배선(2a)과 상기 제2의 금속배선(2b) 사이에 놓여 있는 상기 실리콘산화막(4) 두께를 b라 할때, 부등식 a<b이 성립하는 반도체장치.
- 제1항에 있어서, 상기 실리콘산화막(4)중에는 붕소원자 또는 인원자가 포함되어 있는 반도체장치.
- 제4항에 있어서, 상기 붕소원자 또는 인원자는 5몰%∼10몰% 포함되어 있는 반도체장치.
- 제1항에 있어서, 상기 제1및 제2의 금속배선(2a, 2b)을 피복하는 플라즈마 산화막을 더 포함하는 반도체장치.
- 금속배선(2a, 2b)가 그 위에 형성된 기판(1)을 준비하는 공정, 불소원자가 결합한 실리콘원자를 갖는 원료가 스와 과산화수소와의 혼합가스를 사용하는 화학기상성장법에 의해 상기 금속배선(2a 2b)을 덮도록, 상기 기판(1)상에 실리콘산화막(4)을 형성하는 공정을 포함하는 반도체장치의 제조방법.
- 제7항에 있어서, 상기 원료가스로서, 디플루오르실란을 사용하는 반도체장치의 제조방법.
- 제7항에 있어서, 상기 원료가스로서, 트리플루오르실란 또는 모노플루오르실란을 사용하는 반도체장치의 제조방법.
- 제7항에 있어서, 상기 원료가스로서, 플루오르알콕시실란을 사용하는반도체장치의 제조방법.
- 제7항에 있어서, 상기 실리콘산화막(4)은 -10℃∼100℃의 온도에서 형성되는 반도체장치의 제조방법.
- 제7항에 있어서, 상기 실리콘산화막(4)은 200mTorr∼600Torr의 압력하에서 형성되는 반도체장치의 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7274010A JPH09116011A (ja) | 1995-10-23 | 1995-10-23 | 半導体装置およびその製造方法 |
JP95-274010 | 1995-10-23 |
Publications (2)
Publication Number | Publication Date |
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KR970023759A true KR970023759A (ko) | 1997-05-30 |
KR100259314B1 KR100259314B1 (ko) | 2000-06-15 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1019960030596A KR100259314B1 (ko) | 1995-10-23 | 1996-07-26 | 반도체장치의 제조방법 |
Country Status (5)
Country | Link |
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US (1) | US5703404A (ko) |
JP (1) | JPH09116011A (ko) |
KR (1) | KR100259314B1 (ko) |
DE (1) | DE19612450A1 (ko) |
TW (1) | TW316325B (ko) |
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JPH0951035A (ja) * | 1995-08-07 | 1997-02-18 | Mitsubishi Electric Corp | 層間絶縁膜の形成方法 |
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JP2917897B2 (ja) * | 1996-03-29 | 1999-07-12 | 日本電気株式会社 | 半導体装置の製造方法 |
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JP2962272B2 (ja) * | 1997-04-18 | 1999-10-12 | 日本電気株式会社 | 半導体装置の製造方法 |
US5985770A (en) * | 1997-08-21 | 1999-11-16 | Micron Technology, Inc. | Method of depositing silicon oxides |
JPH1187340A (ja) * | 1997-09-05 | 1999-03-30 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
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JP3132557B2 (ja) * | 1998-04-03 | 2001-02-05 | 日本電気株式会社 | 半導体装置の製造方法 |
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JP2000077402A (ja) * | 1998-09-02 | 2000-03-14 | Tokyo Electron Ltd | プラズマ処理方法および半導体装置 |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03175635A (ja) * | 1989-12-04 | 1991-07-30 | Nec Corp | 半導体装置の多層配線構造体 |
JP2697315B2 (ja) * | 1991-01-23 | 1998-01-14 | 日本電気株式会社 | フッ素含有シリコン酸化膜の形成方法 |
JPH05226480A (ja) * | 1991-12-04 | 1993-09-03 | Nec Corp | 半導体装置の製造方法 |
JP3688726B2 (ja) * | 1992-07-17 | 2005-08-31 | 株式会社東芝 | 半導体装置の製造方法 |
KR0131439B1 (ko) * | 1992-11-24 | 1998-04-14 | 나카무라 타메아키 | 반도체장치 및 그 제조방법 |
JP2917783B2 (ja) * | 1993-12-24 | 1999-07-12 | 日本電気株式会社 | 半導体装置及びその製造方法 |
-
1995
- 1995-10-23 JP JP7274010A patent/JPH09116011A/ja not_active Withdrawn
- 1995-11-14 TW TW084112003A patent/TW316325B/zh active
-
1996
- 1996-03-28 DE DE19612450A patent/DE19612450A1/de not_active Ceased
- 1996-07-26 KR KR1019960030596A patent/KR100259314B1/ko not_active IP Right Cessation
- 1996-12-24 US US08/772,953 patent/US5703404A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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DE19612450A1 (de) | 1997-04-24 |
KR100259314B1 (ko) | 2000-06-15 |
TW316325B (ko) | 1997-09-21 |
US5703404A (en) | 1997-12-30 |
JPH09116011A (ja) | 1997-05-02 |
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