KR970008550A - 정전 파괴 보호 회로를 구비한 반도체 디바이스 - Google Patents

정전 파괴 보호 회로를 구비한 반도체 디바이스 Download PDF

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KR970008550A
KR970008550A KR1019960028677A KR19960028677A KR970008550A KR 970008550 A KR970008550 A KR 970008550A KR 1019960028677 A KR1019960028677 A KR 1019960028677A KR 19960028677 A KR19960028677 A KR 19960028677A KR 970008550 A KR970008550 A KR 970008550A
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semiconductor device
semiconductor chip
common discharge
bonding pad
bonding
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KR1019960028677A
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KR100194312B1 (ko
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기미노리 하야노
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가네꼬 히사시
닛본덴기 가부시끼가이샤
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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/061—Disposition
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    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
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Abstract

반도체 디바이스는 다수의 분리 영역으로 분할된 반도체 칩(10)을 갖고 있다. 이들 각각의 영역에서는 서로 독립한 다수의 공통 방전 라인(12a, 12b, 12c), 각각의 공통 방전 라인에 직접 접속되는 다수의 제1본딩 패드(14a, 14b, 14c), 공통방전 라인에 직접 접속되지 않는 다수의 제2본딩 패드(13a, 13d, 13e, 13h, 13b, 13f, 13c, 13g), 제2본딩 패드와 공통방전 라인 사이에 접속되는 다수의 보호 소자(15a-15h), 및 제1본딩 패드에 직접 접속되고 반도체 칩의 표면에 접착 고정되는 방전용 내부 리드(22)가 구비되어 있다. 본 발명의 모든 실시예에서, 1개 이상의 공통 방전 라인이 있다. 이 배열은 칩의 면적을 축소시키고 설계 자유도를 향상시키며 정전 파괴내성을 향상시킨다.

Description

정전 파괴 보호 회로를 구비한 반도체 디바이스
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제6도는 본 발명에 따른 디바이스의 제1실시예의 평면도.

Claims (4)

  1. 입력 신호에 응답하여 처리된 후 소정의 신호를 출력하기 위한 내부 회로를 구비한 반도체 칩을 갖는 반도체 디바이스에 있어서, 상기 반도체 칩을 분할하여 형성된 다수의 분리 영역, 상기 분리 영역 각각에 제공되는 서로 독립한 공통 방전 라인(12a, 12b, 12c), 상기 공통 방전 라인 각각에 직접 접속되는 제1본딩 패드(14a, 14b, 14c), 상기 공통 방전 라인에 직접 접속되는 것 이외의 제2본딩 패드(13a, 13d, 13e, 13h, 13b, 13f, 13c, 13g), 상기 제2본딩 패드와 공통 방전 라인 사이에 접속되는 보호 소자(15a-15h), 및 상기 제1본딩 패드에 직접 접속되고 상기 반도체 칩의 표면에 접착 고정되는 방전용 내부 리드(22)를 포함하고 있는 것을 특징으로 하는 반도체 디바이스.
  2. 제1항에 있어서, 상기 분리 영역은 상기 반도체 칩의 전체 주변 영역 및 상기 전체 주변 영역 내부의 소정영역으로 이루어지는 것을 특징으로 하는 반도체 디바이스.
  3. 제1항에 있어서, 상기 분리 영역은 상기 반도체 칩의 소정 주변 영역으로 이루어지는 것을 특징으로 하는반도체 디바이스.
  4. 제1항에 있어서, 상기 공통 방전 라인은 상기 제1본딩 패드와 상기 보호 소자 사이에 배치된 소정 부분을갖고, 상기 소정 부분은 상기 제1본딩 패드와 상기 보호 소자를 직접 상호 접속하는 것을 특징으로 하는 반도체 디바이스.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960028677A 1995-07-18 1996-07-16 정전 파괴 보호 회로를 구비한 반도체 디바이스 KR100194312B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP7181348A JP2830783B2 (ja) 1995-07-18 1995-07-18 半導体装置
JP95-181348 1995-07-18

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KR970008550A true KR970008550A (ko) 1997-02-24
KR100194312B1 KR100194312B1 (ko) 1999-06-15

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JP2940506B2 (ja) * 1997-01-31 1999-08-25 日本電気株式会社 半導体装置
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JP2002076282A (ja) 2000-08-30 2002-03-15 Nec Corp 半導体集積回路装置及びその設計方法
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KR100194312B1 (ko) 1999-06-15
JPH0936311A (ja) 1997-02-07
JP2830783B2 (ja) 1998-12-02
US5751051A (en) 1998-05-12

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