KR930018707A - 반도체 장치 - Google Patents

반도체 장치 Download PDF

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Publication number
KR930018707A
KR930018707A KR1019930002010A KR930002010A KR930018707A KR 930018707 A KR930018707 A KR 930018707A KR 1019930002010 A KR1019930002010 A KR 1019930002010A KR 930002010 A KR930002010 A KR 930002010A KR 930018707 A KR930018707 A KR 930018707A
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KR
South Korea
Prior art keywords
die pad
leads
semiconductor device
chip
semiconductor
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Application number
KR1019930002010A
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English (en)
Other versions
KR100299800B1 (ko
Inventor
코지 타니
Original Assignee
사토우 켄이찌로우
롬 가부시끼가이샤
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Application filed by 사토우 켄이찌로우, 롬 가부시끼가이샤 filed Critical 사토우 켄이찌로우
Publication of KR930018707A publication Critical patent/KR930018707A/ko
Application granted granted Critical
Publication of KR100299800B1 publication Critical patent/KR100299800B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Die Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

다이패드 주위에 다수개의 리드들이 정렬되어 있는 리드 프레임의 상기 다이패드에 사각형 반도체 칩에 접착하고, 상기 반도체 칩 및 그 주위의 상기 리드들과의 전기적 접속부를 수지로 봉입성형하되, 상기 반도체 칩과 상기 다이패드의 외주벽 사이의 거리를 상기 칩의 코너에서 보다는 상기 칩의 변중앙부에서 더 크게 하고, 모든 리드선단의 연결선이 상기 다이패드의 외주벽과 대체로 평행하게 되도록 리드를 정렬한 반도체장치.

Description

반도체 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 반도체 칩을 다이패드(die pad)에 접착하는 본 발명의 한 실시예를 도시한 해설도.
제2도는 반도체 칩을 다이패드에 접착하는 본 발명의 다른 실시예를 도시한 해설도.
제3도의 기존의 반도체 장치에 있어서의 다이패드, 반도체 칩 및 리드들의 정렬을 도시한 해설도.
제4도는 리드를 선단을 이은 포락선이 곡선을 이루는 기존의 반도체 장치의 예를 도시한 해설도.

Claims (5)

  1. 다이패드 주위에 다수개의 리드들이 정렬되어 있는 리드 프레임의 상기 다이패드에 사각형 반도체 칩이 접착되고, 상기 반도체 칩 및 그 주위의 상기 리드들과의 접속부가 수지로 봉입성형된 반도체 장치로서, 상기 반도체 칩과 상기 다이패드의 외주벽 사이의 거리는 상기 칩의 코너에서 보다 상기 칩의 변중앙부에서 더 크게하고, 상기 리드들을 모든 리드의 선단을 연결하는 선이 상기 다이패드의 외주벽과 대체로 평행하게끔 배치한 반도체 장치.
  2. 제1항에 있어서, 상기 다이패드가 다각형으로 형성된 반도체 장치.
  3. 제1항에 있어서, 상기 리드들의 선단이 상기 다이패드의 중심으로부터 대체로 같은 거리에 위치한 반도체 장치.
  4. 제1항에 있어서, 상기 다이패드가 8각형의 형상을 갖는 반도체 장치.
  5. 제1항에 있어서, 상기 다이패드가 12각형의 형상을 갖는 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930002010A 1992-02-14 1993-02-13 반도체장치 KR100299800B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP4028208A JPH05226564A (ja) 1992-02-14 1992-02-14 半導体装置
JP92-028208 1992-02-14

Publications (2)

Publication Number Publication Date
KR930018707A true KR930018707A (ko) 1993-09-22
KR100299800B1 KR100299800B1 (ko) 2001-10-22

Family

ID=12242239

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930002010A KR100299800B1 (ko) 1992-02-14 1993-02-13 반도체장치

Country Status (4)

Country Link
US (1) US5468993A (ko)
JP (1) JPH05226564A (ko)
KR (1) KR100299800B1 (ko)
MY (1) MY109587A (ko)

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FR2741191B1 (fr) * 1995-11-14 1998-01-09 Sgs Thomson Microelectronics Procede de fabrication d'un micromodule, notamment pour cartes a puces
JP2765542B2 (ja) * 1995-12-20 1998-06-18 日本電気株式会社 樹脂封止型半導体装置
WO1997027627A1 (en) * 1996-01-25 1997-07-31 Advanced Micro Devices, Inc. Lead frame with circular lead tip layout and improved assembly
DE19717780A1 (de) * 1996-05-01 1997-11-13 Nat Semiconductor Corp Leiterrahmen für eine Halbleiterkomponente
EP0887850A3 (en) 1997-06-23 2001-05-02 STMicroelectronics, Inc. Lead-frame forming for improved thermal performance
SE9900439D0 (sv) 1999-02-09 1999-02-09 Ericsson Telefon Ab L M Electrostatic discharge protection of integrated circuits
US6225685B1 (en) 2000-04-05 2001-05-01 Advanced Micro Devices, Inc. Lead frame design for reduced wire sweep having a defined gap between tie bars and lead pins
US20030151120A1 (en) * 2000-06-28 2003-08-14 Hundt Michael J. Lead-frame forming for improved thermal performance
US6426290B1 (en) 2000-08-18 2002-07-30 Advanced Micro Devices, Inc. Electroplating both sides of a workpiece
US6432291B1 (en) 2000-08-18 2002-08-13 Advanced Micro Devices, Inc. Simultaneous electroplating of both sides of a dual-sided substrate
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JP4102012B2 (ja) * 2000-09-21 2008-06-18 株式会社東芝 半導体装置の製造方法および半導体装置
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JP4767277B2 (ja) * 2008-04-08 2011-09-07 パナソニック株式会社 リードフレームおよび樹脂封止型半導体装置
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CN102244063A (zh) * 2010-05-14 2011-11-16 矽品精密工业股份有限公司 具有多边形芯片座的半导体封装件及其制法
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Also Published As

Publication number Publication date
JPH05226564A (ja) 1993-09-03
MY109587A (en) 1997-02-28
KR100299800B1 (ko) 2001-10-22
US5468993A (en) 1995-11-21

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