KR960002582A - 반도체소자의 제조방법 - Google Patents

반도체소자의 제조방법 Download PDF

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Publication number
KR960002582A
KR960002582A KR1019940015435A KR19940015435A KR960002582A KR 960002582 A KR960002582 A KR 960002582A KR 1019940015435 A KR1019940015435 A KR 1019940015435A KR 19940015435 A KR19940015435 A KR 19940015435A KR 960002582 A KR960002582 A KR 960002582A
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KR
South Korea
Prior art keywords
metal wiring
wiring layer
forming
layer
depositing
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KR1019940015435A
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English (en)
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KR0134108B1 (ko
Inventor
최양규
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940015435A priority Critical patent/KR0134108B1/ko
Priority to GB9512956A priority patent/GB2290906B/en
Priority to CN95106617A priority patent/CN1122955A/zh
Publication of KR960002582A publication Critical patent/KR960002582A/ko
Priority to US08/743,750 priority patent/US5783499A/en
Application granted granted Critical
Publication of KR0134108B1 publication Critical patent/KR0134108B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

본 발명은 초고집적 반도체 소자의 제조방법에 관한 것으로, 특히, 제1금속 배선층 형성후 감광막 패턴을 제거하기 전에 제1금속 배선층이 형성되지 않은 부위에 제1금속 배선층의 높이와 비슷하게 선택적 산화막(Selective Oxide)을 증착시키고 이후에 감광막을 제거하여 완전히 평탄화된 산화막위에 제2금속 배선층을 형성시킴으로써 제2금속 배선층의 신뢰특성을 향상시키는 반도체 소자 제조방법이다.

Description

반도체소자의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 반도체의 각각 다른 기능을 하는 소자들이 이미 형성되어 있고 하부 산화 절연막(1)으로 평탄화 및 절연이 완료되어 있는 상태에서 금속층 패턴을 감광막을 써서 형성하고 감광막을 제거하기 직전의 상태를 도시한 단면도이다,
제2도는 상기 제1도의 상태에서 감광막(3)을 제거하기 전에 선택적 산화막(4)을 제1금속 배선층(2)과 동일한 두께로 증착한 상태의 단면도이다. 상기의 선택적 산화막(4)은 제1금속 배선층(2)이 없는 곳에서, 즉, 하부 산화막(1)이 드러난 곳에서만 증착된다. 증착 두께는 제1금속 배선층과 같아질 정도로 비슷하게 형성한다.
제3도는 선택적 산화막(4)이 증착된 제2도의 상태에서 감광막을 제거한 후의 상태를 도시한 단면도이다.
제4도는 상기 제3도의 상태에서 전체 상부에 산화 절연막(5)을 두껍게 도포한 후, 상기 산화 절연막(5) 상부에 제2금속층(6)을 도포하고 패턴을 형성한 상태의 단면도이다.

Claims (2)

  1. 기판 상부에 각각 고유의 기능을 수행할 수 있는 반도체 소자들을 형성하고, 그 상부에 하부 산화 절연막을 증착하는 단계와, 상기 하부 산화 절연막 상부에 금속을 스퍼터링하여 금속층을 증착시키는 단계와, 상기 금속층 상부에 감광막을 도포하고, 마스크를 이용 노광하여 감광막 패턴을 형성하는 단계와, 상기 감광막 패턴을 이용 상기 금속층을 식각하여 제1금속 배선층을 형성하는 단계와, 감광막 패턴을 제거한 후, 상기 전체 상부에 산화 절연막을 도포하는 단계와, 상기 산화 절연막 상부에 제2속층을 증착시킨 후 패턴을 형성하는 단계를 포함하는 반도체 소자의 제조방법에 있어서, 상기 제1금속 배선층을 형성한 후, 감광막 패턴을 제거하기 전에 제1금속 배선층이 형성되지 않은 곳에 선택적 산화막을 증착하는 단계와, 감광막 패턴을 제거하여 평탄화된 산화막 상부에 제2금속 배선층을 증착하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.
  2. 제1항에 있어서, 상기 선택적 산화막의 두께를 제1금속 배선층의 두께와 비슷하게 증착시키는 것을 특징으로 하는 반도체 소자의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940015435A 1994-06-30 1994-06-30 반도체 소자의 제조방법 KR0134108B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019940015435A KR0134108B1 (ko) 1994-06-30 1994-06-30 반도체 소자의 제조방법
GB9512956A GB2290906B (en) 1994-06-30 1995-06-26 Method for the fabrication of a semiconductor device
CN95106617A CN1122955A (zh) 1994-06-30 1995-06-27 半导体器件的制造方法
US08/743,750 US5783499A (en) 1994-06-30 1996-11-07 Method for the fabrication of a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940015435A KR0134108B1 (ko) 1994-06-30 1994-06-30 반도체 소자의 제조방법

Publications (2)

Publication Number Publication Date
KR960002582A true KR960002582A (ko) 1996-01-26
KR0134108B1 KR0134108B1 (ko) 1998-04-20

Family

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Application Number Title Priority Date Filing Date
KR1019940015435A KR0134108B1 (ko) 1994-06-30 1994-06-30 반도체 소자의 제조방법

Country Status (4)

Country Link
US (1) US5783499A (ko)
KR (1) KR0134108B1 (ko)
CN (1) CN1122955A (ko)
GB (1) GB2290906B (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6593221B1 (en) * 2002-08-13 2003-07-15 Micron Technology, Inc. Selective passivation of exposed silicon

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS581878A (ja) * 1981-06-26 1983-01-07 Fujitsu Ltd 磁気バブルメモリ素子の製造方法
GB8316476D0 (en) * 1983-06-16 1983-07-20 Plessey Co Plc Producing layered structure
JP3469251B2 (ja) * 1990-02-14 2003-11-25 株式会社東芝 半導体装置の製造方法
JPH04359518A (ja) * 1991-06-06 1992-12-11 Nec Corp 半導体装置の製造方法
US5246887A (en) * 1991-07-10 1993-09-21 At&T Bell Laboratories Dielectric deposition
JP2928664B2 (ja) * 1991-08-12 1999-08-03 株式会社東芝 酸化珪素成膜方法およびこの方法に用いる成膜装置
JPH05304202A (ja) * 1992-04-02 1993-11-16 Nec Corp 半導体装置の製造方法
US5504040A (en) * 1992-06-30 1996-04-02 Texas Instruments Incorporated Planarized material layer deposition using condensed-phase processing
JPH0722583A (ja) * 1992-12-15 1995-01-24 Internatl Business Mach Corp <Ibm> 多層回路装置
JPH0770534B2 (ja) * 1993-01-11 1995-07-31 日本電気株式会社 半導体装置の製造方法
JP3152788B2 (ja) * 1993-03-29 2001-04-03 株式会社東芝 半導体装置の製造方法
JPH06333924A (ja) * 1993-05-20 1994-12-02 Fujitsu Ltd 半導体装置の製造方法
US5382545A (en) * 1993-11-29 1995-01-17 United Microelectronics Corporation Interconnection process with self-aligned via plug
CA2131668C (en) * 1993-12-23 1999-03-02 Carol Galli Isolation structure using liquid phase oxide deposition
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US5661051A (en) * 1996-10-09 1997-08-26 National Science Council Method for fabricating a polysilicon transistor having a buried-gate structure

Also Published As

Publication number Publication date
KR0134108B1 (ko) 1998-04-20
US5783499A (en) 1998-07-21
GB2290906B (en) 1998-03-25
GB9512956D0 (en) 1995-08-30
GB2290906A (en) 1996-01-10
CN1122955A (zh) 1996-05-22

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