CN1122955A - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

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Publication number
CN1122955A
CN1122955A CN95106617A CN95106617A CN1122955A CN 1122955 A CN1122955 A CN 1122955A CN 95106617 A CN95106617 A CN 95106617A CN 95106617 A CN95106617 A CN 95106617A CN 1122955 A CN1122955 A CN 1122955A
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metal
layer
deposit
oxide layer
semiconductor device
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崔圭
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SK Hynix Inc
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Hyundai Electronics Industries Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

通过在有用于在下氧化层上形成第一金属布线层的光刻胶膜图形的情况下，使选择的氧化层生长到第一金属布线厚度得到的平整化层上淀积一绝缘层，来制造无空隙的双平面金属结构。此外，由于第一金属布线的平整化层，使对在该绝缘层上所淀积的第二金属层的刻图步骤可容易进行，使生产率显著提高。因而本发明可有效地用于设计标准小于0.4μm的超大规模集成器件。

Description

半导体器件的制造方法
本发明一般涉及一种采用多层金属布线结构的半导体器件的制造方法，特别涉及高集成化和半导体器件的生产率。
通常，通过在一绝缘层上淀积一第一金属层；使用金属布线掩模刻蚀第一金属层形成第一金属布线；淀积一铺垫平整化绝缘膜以及在第一金属层上淀积一第二金属层来制造适用于半导体器件的双平面金属结构。这些常规的工艺步骤的显著缺陷是当由于第一金属布线间的深槽产生大长宽比时出现空隙，严重影响器件特性。此外，在第一金属布线上所淀积的绝缘层不完全平整，很难进行第二金属层的刻图步骤，因而降低了生产率。
所以，本发明的主要目的在于提供通过选择生长氧化物，避开上述与已有技术相关的问题来制造采用多层金属布线结构的半导体器件的方法。
本发明的另一个目的在于提供一种采用多层金属布线且无空隙的结构的半导体器件的制造方法。
本发明的再一个目的在于提供一种能显著提高器件集成度的制造方法。
通过参照附图详细地说明本发明的优选实施例会更加明了本发明的上述目的及其它优点。
图1～4是表示根据本发明形成半导体器件中的多层金属布线结构工艺步骤的剖面图。
参照附图会更了解本发明优选实施例的用途，例中描述的是双层金属布线，其中相同的标号分别用于相同的和相应的部件。
首先，图1表示在下平整化氧化层1上所形成的第一金属布线2，下平整化氧化层1是器件例如半导基底(未示出)上的晶体管上的一层绝缘层。如从该图所见，以光刻胶膜图形3作为掩模刻蚀下氧化层1上所淀积的第一金属层制成第一金属布线2。
图2是在下氧化层的裸露表面上生长选择氧化层4之后的剖面图，其厚等于第一金属布线2的高度。
图3是在去掉光刻胶膜图形3后获得的选择氧化层4与第一金属布线2交替的平整化层之后剖面图。
最后，图4是在平整化层上全面淀积一绝缘层5，随后在该绝缘层5上淀积第二金属层6之后的剖面图。
如前文所述，根据本发明，通过在有用于在下氧化层上形成第一金属布线的光刻胶膜图形的情况下，使选择氧化层生长到第一金属布线厚度所得到的平整化层上淀积一绝缘层，可防止空隙发生。此外，由于第一金属布线的平整化层，使对第二金属层的刻图步骤可容易进行，使生产率显著提高。因而，本发明可有效地用于设计标准小于0.4μm的超大规模集成器件。
前文已描述了一种用于制造采用双平面金属结构的半导体器件的技术，但预计对本领域的技术人员可提示其它等同构形、改型、及替代的实施方案。例如，在金属层淀积之前通过生长此类选择氧化层，可使用该技术形成三层金属和更多的多平面金属结构。所以在本发明的精神内，虽然本文未明确地提及，也可创立替代的实施方案，本发明仅由所附权利要求的范畴和内函限定。

Claims (2)

1.一种制造采用多层金属布线结构的半导体器件的制造方法，该法包括以下各步骤：
在一半导体基片顶上的晶体管结构上淀积一下氧化层；
在该下氧化层上淀积第一金属层，并在该第一金属层上形成光刻胶膜图形；
用该光刻胶膜图形作掩模刻蚀第一金属层，形成第一金属布线；
在下氧化层的裸露区域上生长选择的氧化层；
去掉光刻胶膜图形，并在所得结构上淀积铺垫绝缘层；以及
在该绝缘层上淀积第二金属层。
2.一种根据权利要求1的方法，使其中所说的选择氧化层生长到与所说的第二金属层高度相同的厚度。
CN95106617A 1994-06-30 1995-06-27 半导体器件的制造方法 Pending CN1122955A (zh)

Applications Claiming Priority (2)

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KR1019940015435A KR0134108B1 (ko) 1994-06-30 1994-06-30 반도체 소자의 제조방법
KR94-15435 1994-06-30

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CN1122955A true CN1122955A (zh) 1996-05-22

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US6593221B1 (en) * 2002-08-13 2003-07-15 Micron Technology, Inc. Selective passivation of exposed silicon

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS581878A (ja) * 1981-06-26 1983-01-07 Fujitsu Ltd 磁気バブルメモリ素子の製造方法
GB8316476D0 (en) * 1983-06-16 1983-07-20 Plessey Co Plc Producing layered structure
JP3469251B2 (ja) * 1990-02-14 2003-11-25 株式会社東芝 半導体装置の製造方法
JPH04359518A (ja) * 1991-06-06 1992-12-11 Nec Corp 半導体装置の製造方法
US5246887A (en) * 1991-07-10 1993-09-21 At&T Bell Laboratories Dielectric deposition
JP2928664B2 (ja) * 1991-08-12 1999-08-03 株式会社東芝 酸化珪素成膜方法およびこの方法に用いる成膜装置
JPH05304202A (ja) * 1992-04-02 1993-11-16 Nec Corp 半導体装置の製造方法
US5504040A (en) * 1992-06-30 1996-04-02 Texas Instruments Incorporated Planarized material layer deposition using condensed-phase processing
JPH0722583A (ja) * 1992-12-15 1995-01-24 Internatl Business Mach Corp <Ibm> 多層回路装置
JPH0770534B2 (ja) * 1993-01-11 1995-07-31 日本電気株式会社 半導体装置の製造方法
JP3152788B2 (ja) * 1993-03-29 2001-04-03 株式会社東芝 半導体装置の製造方法
JPH06333924A (ja) * 1993-05-20 1994-12-02 Fujitsu Ltd 半導体装置の製造方法
US5382545A (en) * 1993-11-29 1995-01-17 United Microelectronics Corporation Interconnection process with self-aligned via plug
CA2131668C (en) * 1993-12-23 1999-03-02 Carol Galli Isolation structure using liquid phase oxide deposition
US5612239A (en) * 1995-08-24 1997-03-18 United Microelectronics Corporation Use of oxide spacers formed by liquid phase deposition
US5661051A (en) * 1996-10-09 1997-08-26 National Science Council Method for fabricating a polysilicon transistor having a buried-gate structure

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GB2290906B (en) 1998-03-25
KR0134108B1 (ko) 1998-04-20
KR960002582A (ko) 1996-01-26
GB2290906A (en) 1996-01-10
GB9512956D0 (en) 1995-08-30
US5783499A (en) 1998-07-21

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