KR950030393A - 박막 트랜지스터의 제조방법, 박막 트랜지스터 및 액정표시장치 - Google Patents

박막 트랜지스터의 제조방법, 박막 트랜지스터 및 액정표시장치 Download PDF

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KR950030393A
KR950030393A KR1019950010655A KR19950010655A KR950030393A KR 950030393 A KR950030393 A KR 950030393A KR 1019950010655 A KR1019950010655 A KR 1019950010655A KR 19950010655 A KR19950010655 A KR 19950010655A KR 950030393 A KR950030393 A KR 950030393A
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semiconductor layer
gate insulating
layer
thin film
film transistor
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다케시 가시로
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사토 후미오
가부시키가이샤 도시바
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Abstract

본 발명은 박막 트랜지스터의 제조방법, 특히 액정표시장치의 스위칭소자로서 사용되는 박막 트랜지스터의 제조방법에 관한 것으로서, 양호한 특성을 갖는 고품질 TFT의 제조방법을 얻는 것을 목적으로 하며, 박막 트랜지스터의 게이트 절연층(3)및 반도체층(4)을 플라즈마 CVD법에 의해 적층 형성하는 박막 트랜지스터의 제조방법에 있어서, 게이트 절연층상에 반도체층을 적층형성할 때에 게이트 절연층을 형성한 후 플라즈마 방전을 유지한 채로 방전전극의 간격을 변화시키고, 그 후 반도체층을 형성하도록 한 것을 특징으로 한다.

Description

박막 트랜지스터의 제조방법, 박막 트랜지스터 및 액정표시장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 실시예 1에 관한 박막 트랜지스터의 구성을 나타내는 도면, 제2도는 제2(a)도 내지 제2(e)도는 각각 상기 박막 트랜지스터의 제조방법을 설명하기 위한 도면.

Claims (17)

  1. 게이트 절연층 및 이 게이트 절연층상에 적층형성된 반도체층을 갖는 박막트랜지스터의 상기 게이트 절연층 및 반도체층을 플라즈마 CVD법에 의해 적층 형성하는 박막 트랜지스터의 제조방법에 있어서, 상기 게이트 절연층상에 상기 반도체층을 적층 형성할 때에 상기 게이트 절연층을 형성한 후 플라즈마 방전을 유지한 채로 방전전극의 간격을 변화시키고, 그 후 반도체층을 형성하는 것을 특징으로 하는 박막 트랜지스터의 제조방법.
  2. 제1항에 있어서, 게이트 절연층상에 반도체층을 적층 형성할 때에 상기 게이트 절연층을 형성한 후 H2가스와 플라즈마 방전을 유지한 채로 방전전극의 간격을 변화시키고, 그 후 상기 반도체층을 형성하는 것을 특징으로 하는 박막 트랜지스터의 제조방법.
  3. 제1항에 있어서, 게이트 절연층상에 반도체층을 적층하여 형성할 때에 상기 게이트 절연층을 형성한 후 막을 형성하지 않는 가스를 주성분으로 한 플라즈마 방전을 유지한 채로 방전전극의 간격을 변화시키고, 그 후 상기 반도체층을 형성하는 것을 특징으로 하는 박막 트랜지스터의 제조방법.
  4. 제1항에 있어서, 게이트 절연층상에 반도체층을 적층 형성할 때에 상기 게이트 절연층을 형성한 후 H2, He, Ar, N2, NH3가스 중 적어도 1가지 종류의 가스를 주성분으로 한 플라즈마방전을 유지한 채로 방전전극이 간격을 변화시키고, 그 후 상기 반도체층을 형성하는 것을 특징으로 하는 박막 트랜지스터의 제조방법.
  5. 제1항에 있어서, 게이트 절연층상에 반도체층을 적층 형성할 때에 상기 게이트 절연층을 형성한 후 상기 게이트 절연층 형성시의 압력보다도 저압의 방전기간을 두며, 또한 플라즈마 방전을 유지한 채로 방전전극의 간격을 변화시키고, 그 후 상기 반도체층을 형성하는 것을 특징으로 하는 박막 트랜지스터의 제조방법.
  6. 반도체층 및 이 반도체층상에 적층 형성된 반도체 보호층을 갖는 박막 트랜지스터의 상기 반도체층 및 반도체 보호층을 플라즈마 CVD법에 의해 적층 형성하는 박막 트랜지스터의 제조방법에 있어서, 상기 반도체층상에 상기 반도체 보호층을 적층 형성할 때에 상기 반도체층을 형성한 후 플라즈마 방전을 유지한 채로 방전 전극의 간격을 변화시키고, 그 후 상기 반도체 보호층을 형성하는 것을 특징으로 하는 박막 트랜지스터의 제조방법.
  7. 제6항에 있어서, 반도체층상에 반도체 보호층을 적층 형성할 때에 상기 반도체층을 형성한 후 H2가스의 플라즈마 방전을 유지한 채로 방전전극의 간격을 변화시키고, 그 후 상기 반도체 보호층을 형성하는 것을 특징으로 하는 박막 트랜지스터의 제조방법.
  8. 제6항에 있어서, 반도체층상에 반도체 보호층을 적층 형성할 때에 상기 반도체층을 형성한 후 막을 형성하지 않는 가스를 주성분으로 한 플라즈마 방전을 유지한 채로 방전전극의 간격을 변화시키고, 그 후 상기 반도체 보호층을 형성하는 것을 특징으로 하는 박막 트랜지스터의 제조방법.
  9. 제6항에 있어서, 반도체층상에 반도체 보호층을 적층 형성할 때에 상기 반도체층을 형성한 후 H2, He, Ar, N2, NH3가스 중 적어도 1가지 종류의 가스를 주성분으로 한 플라즈마방전을 유지한 채로 방전전극의 간격을 변화시키고, 그 후 상기 반도체층을 형성하는 것을 특징으로 하는 박막 트랜지스터의 제조방법.
  10. 제6항에 있어서, 반도체층상에 반도체 보호층을 적층 형성할 때에 상기 반도체층을 형성한 후 상기 반도체층 형성시의 압력보다도 저압의 방전기간을 두며, 또한 플라즈마 방전을 유지한 채로 방전전극의 간격을 변화시카고, 그 후 상기 반도체 보호층을 형성하는 것을 특징으로 하는 박막 트랜지스터의 제조방법.
  11. 반도체층 및 이 반도체층상에 적층 형성된 게이트 절연층을 갖는 박막 트랜지스터의 상기 반도체층 및 게이트 절연층을 플라즈마 CVD법에 의해 적층 형성하는 박막 트랜지스터의 제조방법에 있어서, 상기 반도체층상에 상기 게이트 절연층을 적층 형성할 때에 상기 반도체층을 형성한 후 플라즈마 방전을 유지한 채로 방전 전극의 간격을 변화시키고, 그 후 상기 게이트 절연층을 형성하는 것을 특징으로 하는 박막 트랜지스터의 제조방법.
  12. 제11항에 있어서, 반도체층상에 게이트 절연층을 적층 형성할 때에 상기 반도체층을 형성한 후 H2가스의 플라즈마 방전을 유지한 채로 방전전극의 간격을 변화시키고, 그 후 상기 게이트 절연층을 형성하는 것을 특징으로 하는 박막 트랜지스터의 제조방법.
  13. 제11항에 있어서, 반도체층상에 게이트 절연층을 적층 형성할 때에 상기 반도체층을 형성한 후 막을 형성하지 않는 가스를 주성분으로 한 플라즈마 방전을 유지한 채로 방전전극의 간격을 변화시키고, 그 후 상기 게이트 절연층을 형성하는 것을 특징으로 하는 박막 트랜지스터의 제조방법.
  14. 제11항에 있어서, 반도체층상에 게이트 절연층을 적층 형성할 때에 상기 반도체층을 형성한 후 H2, He, Ar, N2, NH3가스 중 적어도 1가지 종류의 가스를 주성분으로 한 플라즈마 방전을 유지한 채로 방전전극의 간격을 변화시키고, 그 후 상기 게이트 절연층을 형성하는 것을 특징으로 하는 박막 트랜지스터의 제조방법.
  15. 제11항에 있어서, 반도체층상에 게이트 절연층을 적층 형성할 때에 상기 반도체층을 형성한 후 상기 반도체층 형성시의 압력보다도 저압의 방전기간을 두며, 또한 플라즈마 방전을 유지한 채로 방전전극의 간격을 변화시카고, 그 후 상기 게이트 절연층을 형성하는 것을 특징으로 하는 박막 트랜지스터의 제조방법.
  16. 제1항 내지 제15항 중 어느 한 항에 기재한 박막 트랜지스터의 제조방법에 의해 제작된 것을 특징으로 하는 박막 트랜지스터.
  17. 제16항에 기재한 박막 트랜지스터를 스위치 소자로서 사용한 것을 특징으로 하는 액정표시장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
KR1019950010655A 1994-04-26 1995-04-25 박막 트랜지스터의 제조방법, 박막 트랜지스터 및 액정표시장치 KR0156060B1 (ko)

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