KR940022820A - 패키지 성형용 금형 및 그 금형을 이용한 플라스틱 고체촬상소자 패키지 제조방법 및 패키지 - Google Patents

패키지 성형용 금형 및 그 금형을 이용한 플라스틱 고체촬상소자 패키지 제조방법 및 패키지 Download PDF

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KR940022820A
KR940022820A KR1019930003229A KR930003229A KR940022820A KR 940022820 A KR940022820 A KR 940022820A KR 1019930003229 A KR1019930003229 A KR 1019930003229A KR 930003229 A KR930003229 A KR 930003229A KR 940022820 A KR940022820 A KR 940022820A
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package
mold
chip
lead frame
semiconductor chip
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KR1019930003229A
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KR960009089B1 (ko
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전흥섭
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문정환
금성일렉트론 주식회사
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Priority to KR1019930003229A priority Critical patent/KR960009089B1/ko
Priority to JP03354894A priority patent/JP3394313B2/ja
Publication of KR940022820A publication Critical patent/KR940022820A/ko
Priority to US08/624,204 priority patent/US5644169A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Moulds For Moulding Plastics Or The Like (AREA)
  • Injection Moulding Of Plastics Or The Like (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Light Receiving Elements (AREA)

Abstract

본 발명은 패키지 성형용 금형 및 그 금형을 이용한 플라스틱 고체촬상소자 패키지 제조방법 및 패키지에 관한 것으로, 리드프레임의 패들 위에 반도체칩을 부착고정하고, 상기 칩과 리드프레임의 인너리드를 금속 와이어로 접속연결하여 전기적인 신호전달체계를 구성한 반조립품 상태의 제품을 상부몰드다이의 캐비티 중간부에 돌출부가 형성된 구조의 금형을 이용하여 트랜스퍼 몰딩함으로써 칩의 수광영역부 상부가 오픈된 패키지 몸체를 형성한 후, 상기 패키지 몸체의 개구부 상단부에 빛투과용 글래스리드를 탑재하여 구성한 것인바, 저가이면서도 성형성이 우수한 플라스틱수지를 이용하여 패키징함으로써 제조원가가 절감되고, 생산성이 향상되며, 또한 패키지 제조공정이 보다 간소화되는 등의 효과가 있다.

Description

패키지 성형용 금형 및 그 금형을 이용한 플라스틱 고체촬상소자 패키지 제조방법 및 패키지
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도 내지 제5도는 본 발명을 설명하기 위한 도면으로서, 제3도는 본 발명에 의한 플라스틱 고체촬상소자 패키지의 구조를 보인 종단면도이고, 제4도는 본 발명에 의한 플라스틱 고체촬상소자 패키지의 제조 공정도이며, 제5도는 본 발명 플라스틱 고체촬상소자 패키지의 몰딩공정에 사용되는 금형의 구조를 보인 요부 확대 단면도이다.

Claims (6)

  1. 하부몰드다이(21)의 상부에 결합되는 상부몰드다이(22)의 캐비티(22a) 중간부에 몰딩시 반도체칩(11)의 수광영역부(11a) 상부가 오픈되도록 소정형상의 돌출부(23)를 형성하여서 된 패키지 성형용 금형.
  2. 제1항에 있어서, 상기 돌출부(23)의 하면 가장자리에는 반도체칩(11)의 수광영여부(11a)내로 몰드수지가 침입하는 것을 방지하기 위한 수지침투방지턱부(23a)가 형성되고, 이 수지침투방지턱부(23a)와 반도체칩(11)의 접촉면 사이에는 금형의 가압력을 완화시키기 위한 완충부재가 개재됨을 특징으로 하는 패키지 성형용 금형.
  3. 제2항에 있어서, 상기 완충부재는 칩상면의 수지침투방지턱부(23a) 접촉면에 폴리머계열의 수지가 코팅 또는 라미네이션된 것을 특징으로 하는 패키지 성형용 금형.
  4. 소잉공정에 의해 개개로 분리된 칩을 리드프레임의 패들 위에 부착고정하는 다이어태치 공정과, 상기 반도체칩과 리드프레임의 인너리드를 금속와이어로 접속연결하여 전기적인 신호전달체계를 구성하는 와이어 본딩 공정과, 와이어본딩된 칩과 리드프레임의 인너리드를 포함하는 일정면적을 상부몰드다이의 캐비티 중간부에 돌출부가 형성된 구조의 금형을 이용하여 칩의 수광영역부 상부가 오픈되도록 몰드수지로 몰딩하여 개구부를 가지는 패키지 몸체를 형성하는 몰딩공정과, 상기 패키지 몸체의 개구부 상단부에 빛투과용 글래스리드를 탑재하고 밀봉하는 글래스리드실링공정과, 통상적인 플래팅공정 및 트림/포밍공정으로 진행함을 특징으로 하는 플라스틱 고체촬상소자 패키지 제조방법.
  5. 반도체칩(11)과, 상기 반도체칩(11)이 부착고정되는 패들(12a) 및 상기 칩(11)에 연결되는 다수개의 인/아웃리드(12b)(12c)를 가지는 리드프레임(12)과, 상기 칩(11)과 리드프레임(12)의 인너리드(12b)를 전기적으로 접속연결시키기 위한 금속와이어(13)와, 상기 칩(11)과 리드프레임(12)의 인너리드(12b)를 포함하는 일정면적을 에워싸도록 형성되고 중간부에는 칩(11)의 수광영역부(11a) 상부를 노출시키기 위한 개구부(14a)가 구비된 패키지몸체(14)와, 상기 패키지몸체(14)의 개구부(14a) 상단에 탑재된 빛투과용 글래스리드(15)로 구성함을 특징으로 하는 플라스틱 고체촬상소자 패키지.
  6. 제5항에 있어서, 상기 패키지몸체(14)의 개구부(14a) 상단에는 글래스리드 (15)의 탑재를 용이하게 함과 아울러 보다 효과적인 실링을 위한 탄력부(14b)가 형성된 것을 특징으로 하는 플라스틱 고체촬상소자 패키지.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930003229A 1993-03-04 1993-03-04 패키지 성형용 금형 및 그 금형을 이용한 플라스틱 고체촬상소자 패키지 제조방법 및 패키지 KR960009089B1 (ko)

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Application Number Priority Date Filing Date Title
KR1019930003229A KR960009089B1 (ko) 1993-03-04 1993-03-04 패키지 성형용 금형 및 그 금형을 이용한 플라스틱 고체촬상소자 패키지 제조방법 및 패키지
JP03354894A JP3394313B2 (ja) 1993-03-04 1994-03-03 半導体パッケージの成形用金型を利用した半導体パッケージの製造方法および半導体パッケージ
US08/624,204 US5644169A (en) 1993-03-04 1996-04-03 Mold and method for manufacturing a package for a semiconductor chip and the package manufactured thereby

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KR1019930003229A KR960009089B1 (ko) 1993-03-04 1993-03-04 패키지 성형용 금형 및 그 금형을 이용한 플라스틱 고체촬상소자 패키지 제조방법 및 패키지

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KR940022820A true KR940022820A (ko) 1994-10-21
KR960009089B1 KR960009089B1 (ko) 1996-07-10

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