KR940022811A - 세라믹제 어댑터 세라믹 패키지 - Google Patents
세라믹제 어댑터 세라믹 패키지 Download PDFInfo
- Publication number
- KR940022811A KR940022811A KR1019940005715A KR19940005715A KR940022811A KR 940022811 A KR940022811 A KR 940022811A KR 1019940005715 A KR1019940005715 A KR 1019940005715A KR 19940005715 A KR19940005715 A KR 19940005715A KR 940022811 A KR940022811 A KR 940022811A
- Authority
- KR
- South Korea
- Prior art keywords
- ceramic
- accommodating
- portions
- semiconductor chip
- package
- Prior art date
Links
- 239000000919 ceramic Substances 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract 13
- 239000004020 conductor Substances 0.000 claims 4
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- A—HUMAN NECESSITIES
- A01—AGRICULTURE; FORESTRY; ANIMAL HUSBANDRY; HUNTING; TRAPPING; FISHING
- A01K—ANIMAL HUSBANDRY; AVICULTURE; APICULTURE; PISCICULTURE; FISHING; REARING OR BREEDING ANIMALS, NOT OTHERWISE PROVIDED FOR; NEW BREEDS OF ANIMALS
- A01K97/00—Accessories for angling
- A01K97/12—Signalling devices, e.g. tip-up devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Life Sciences & Earth Sciences (AREA)
- Environmental Sciences (AREA)
- Power Engineering (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Animal Husbandry (AREA)
- Biodiversity & Conservation Biology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Connecting Device With Holders (AREA)
Abstract
고밀도 실장이 가능한, 반도체 칩을 수납하기 위한 육면체의 세라믹 패키지를 제공한다.
세라믹 패키지(30)은 (가) 적층된 복수의 저온 소성 세라믹 시트(12)로 이루어지고, (나) 상면(30A) 및 하면(30B)의 각각에 형성된 반도체 칩을 수납하는 수납부(32A,32B)와, (다) 이들 수납부 각각에 형성된 반도체 칩과의 전기적 접속을 위한 접속부(17A,18B)와, (라) 하면(32B)에 형성된 복수의 랜드부(14)와, (마) 내부에 형성된 랜드부(14)와 접속부(18A,18B) 혹은 접속부(18A,18B) 서로를 전기적으로 접속하는 도체 회로부(16)을 구비하고 있다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 실시예1의 세라믹제 어댑터의 개략적 단면도, 제2도는 실시예1의 세라믹제 어댑터를 이용한 LGA패키지로서 프린트 배선판과의 접속 상태를 도시하는 개략적 단면도이다.
Claims (6)
- 반도체 패키지와 프린터를 전기적으로 접속하기 위한 육면체의 세라믹제 어댑터에 있어서, 적층된 복수의 저온 소성 세라믹 시트로 이루어지며, 상면 및 하면의 각각에 형성된 복수의 랜드부와, 내부에 형성된 랜드부 서로를 전기적으로 접속하는 반도체 회로부를 구비하는 있는 것을 특징으로 하는 세라믹제 어댑터.
- 프린트 배선판에 설치된 회로와, 단자부를 위로 향한 상태에서 프린트 배선판에 부착된 반도체 칩을 전기적으로 접속하기 위한 육면체의 세라믹제 어댑터에 있어서, 적층된 복수의 저온 소성 세라믹 시트로 이루어지며, 하면에 형성된 프린트 배선판의 회로와의 전기적 접속을 위한 복수의 랜드부와, 하면에 형성된 반도체 칩을 수납하기 위한 요부와, 상기 요부에 형성된 반도체 칩의 단자부와의 전기적 접속을 위한 접속부와, 내부에 형성된 접속부와 랜드부를 전기적으로 접속하는 도체 회로부를 구비하고 있는 것을 특징으로 하는 세라믹제 어댑터.
- 반도체 칩을 수납하기 위한 육면체의 세라믹 패키지에 있어서, 적층된 복수의 저온 소성 세라믹 시트로 이루어지며, 상면 및 하면의 각각에 형성된 반도체 칩을 수납하는 수납부와, 상기 수납부의 각각에 형성된 반도체 칩의 전기적 접속을 위한 접속부와, 하면에 형성된 복수의 랜드부와, 내부에 형성된 랜드부와 접속부 혹은 접속부 서로를 전기적으로 접속하는 도체 회로부를 구비하고 있는 것을 특징으로 하는 세라믹 패키지.
- 반도체 칩을 수납하기 위한 육면체의 세라믹 패키지에 있어서, 적층된 복수의 저온 소성 세라믹 시트로 이루어지며, 반도체 칩을 수납하는 수납부와, 상기 수납부에 형성된 반도체 칩과의 전기적 접속을 위한 접속부와, 상면 및 하면의 각각에 형성된 복수개의 랜드부와, 내부에 형성된 각각의 랜드부와 접속부 혹은 랜드부 사로를 전기적으로 접속하는 도체 회로부를 구비하고 있는 것을 특징으로 하는 세라믹 패키지.
- 제4항에 있어서, 상기 수납부는 세라믹 패키지의 상면 혹은 하면에 형성된 요부로 이루어지는 것을 특징으로 하는 세라믹 패키지.
- 제4항에 있어서, 상기 수납부는 세라믹 패키지의 상면 혹은 하면에 형성된 요부로 이루어지며, 세라믹 패키지의 내부에 형성된 도체 회로부는 반도체 칩 서로를 전기적으로 접속하기 위한 회로를 더 포함하고 있는 것을 특징으로 하는 세라믹 패키지.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP93-086837 | 1993-03-23 | ||
JP5086837A JPH06275739A (ja) | 1993-03-23 | 1993-03-23 | セラミック製アダプター及びセラミックパッケージ |
Publications (1)
Publication Number | Publication Date |
---|---|
KR940022811A true KR940022811A (ko) | 1994-10-21 |
Family
ID=13897930
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940005715A KR940022811A (ko) | 1993-03-23 | 1994-03-22 | 세라믹제 어댑터 세라믹 패키지 |
Country Status (2)
Country | Link |
---|---|
JP (1) | JPH06275739A (ko) |
KR (1) | KR940022811A (ko) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5500628A (en) * | 1995-01-24 | 1996-03-19 | Motorola, Inc. | Double-sided oscillator package and method of coupling components thereto |
JP2002100704A (ja) * | 1995-02-09 | 2002-04-05 | Kyocera Corp | パッケージおよびその実装構造 |
JPH09199824A (ja) * | 1995-11-16 | 1997-07-31 | Matsushita Electric Ind Co Ltd | プリント配線板とその実装体 |
TW338180B (en) * | 1996-03-29 | 1998-08-11 | Mitsubishi Electric Corp | Semiconductor and its manufacturing method |
JP3305574B2 (ja) * | 1996-06-24 | 2002-07-22 | 京セラ株式会社 | 配線基板 |
JP3314139B2 (ja) * | 1996-09-27 | 2002-08-12 | 京セラ株式会社 | 半導体装置 |
JP3793547B2 (ja) * | 1997-05-28 | 2006-07-05 | 京セラ株式会社 | 積層セラミック回路基板の製造方法 |
FR2772516B1 (fr) * | 1997-12-12 | 2003-07-04 | Ela Medical Sa | Circuit electronique, notamment pour un dispositif medical implantable actif tel qu'un stimulateur ou defibrillateur cardiaque, et son procede de realisation |
JPH11274344A (ja) * | 1998-03-20 | 1999-10-08 | Nec Kansai Ltd | 電子素子封止用パッケージ及び電子素子封止構体 |
JP3758066B2 (ja) * | 1999-06-08 | 2006-03-22 | 三菱電機株式会社 | 半導体装置とその製造方法 |
JP2002329803A (ja) * | 2001-04-27 | 2002-11-15 | Mitsubishi Electric Corp | 電子回路モジュールおよびその製造方法 |
US7061102B2 (en) * | 2001-06-11 | 2006-06-13 | Xilinx, Inc. | High performance flipchip package that incorporates heat removal with minimal thermal mismatch |
JP3870778B2 (ja) * | 2001-12-20 | 2007-01-24 | ソニー株式会社 | 素子内蔵基板の製造方法および素子内蔵基板 |
JP4128945B2 (ja) * | 2003-12-04 | 2008-07-30 | 松下電器産業株式会社 | 半導体装置 |
JP4511311B2 (ja) * | 2004-10-28 | 2010-07-28 | 京セラ株式会社 | 多数個取り配線基板および電子装置 |
JP4451790B2 (ja) * | 2005-01-06 | 2010-04-14 | パナソニック株式会社 | 半導体装置、半導体装置の製造方法およびカード型記録媒体 |
JP2006319136A (ja) * | 2005-05-12 | 2006-11-24 | Mitsubishi Electric Corp | 高周波モジュール |
JP2005354093A (ja) * | 2005-07-15 | 2005-12-22 | Kyocera Corp | 電子部品実装基板およびその製造方法 |
JP2006148177A (ja) * | 2006-03-06 | 2006-06-08 | Kyocera Corp | 積層セラミック回路基板 |
JP2008263150A (ja) * | 2007-04-16 | 2008-10-30 | Matsushita Electric Ind Co Ltd | 半導体装置および検査方法 |
JP2007251192A (ja) * | 2007-05-07 | 2007-09-27 | Kyocera Corp | 電子部品実装基板 |
JP2008072151A (ja) * | 2007-12-03 | 2008-03-27 | Kyocera Corp | 回路基板 |
KR101209306B1 (ko) * | 2010-06-23 | 2012-12-06 | 엘지이노텍 주식회사 | 세라믹 기판 및 그의 제조 방법과 이미지 센서 패키지 및 그의 제조 방법 |
JP6848209B2 (ja) * | 2016-05-13 | 2021-03-24 | 大日本印刷株式会社 | 実装基板及びそれを備える電子機器 |
JP6981884B2 (ja) * | 2018-01-22 | 2021-12-17 | 京セラ株式会社 | 配線基板、パッケージおよび電子装置 |
JP2019133987A (ja) * | 2018-01-29 | 2019-08-08 | 京セラ株式会社 | 電子部品収納用基板およびこれを用いたパッケージ |
-
1993
- 1993-03-23 JP JP5086837A patent/JPH06275739A/ja active Pending
-
1994
- 1994-03-22 KR KR1019940005715A patent/KR940022811A/ko not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
JPH06275739A (ja) | 1994-09-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR940022811A (ko) | 세라믹제 어댑터 세라믹 패키지 | |
US4734819A (en) | Decoupling capacitor for surface mounted leadless chip carrier, surface mounted leaded chip carrier and pin grid array package | |
US4164003A (en) | Integrated circuit package and connector therefor | |
US5027191A (en) | Cavity-down chip carrier with pad grid array | |
KR930006816A (ko) | 반도체 장치 및 그 제조방법 | |
US5260601A (en) | Edge-mounted, surface-mount package for semiconductor integrated circuit devices | |
TW429560B (en) | Heatspreader for a flip chip device, and method for connecting the heatspreader | |
KR970067801A (ko) | 반도체 장치 및 그 제조방법 | |
CA2139266A1 (en) | Semiconductor Package | |
KR930014929A (ko) | 반도체 장치 및 그의 제조 방법 | |
KR930005177A (ko) | 3차원 멀티칩 모듈형 집적회로 | |
DE3678023D1 (de) | Integrierte schaltungsanordnung mit gestapelten leiterschichten zum verbinden von schaltungselementen. | |
KR960705363A (ko) | 집적회로장치(integrated circuit device) | |
KR900017449A (ko) | 전자 어셈블리 및 전자 어셈블리를 형성하는 공정 | |
KR950028581A (ko) | 전도 부재에 전기적으로 결합되는 이중 기층 패키지 어셈블리 | |
KR890015160A (ko) | 카드구조 및 ic카드 | |
KR890013751A (ko) | 반도체 장치 | |
US4600968A (en) | Semiconductor device package having regions of different thermal properties | |
US4949220A (en) | Hybrid IC with heat sink | |
US4885662A (en) | Circuit module connection system | |
KR960012455A (ko) | 접속 핀을 통해 기판과 캡에 접속된 전자 부품을 탑재하는 멀티 칩 세라믹 모듈 | |
US7438558B1 (en) | Three-dimensional stackable die configuration for an electronic circuit board | |
KR940008054A (ko) | 반도체 패키지의 실장구조 | |
US20020055283A1 (en) | Multiple line grid connector | |
KR910019222A (ko) | 고집적 반도체 장치 및 이를 사용한 반도체 모듈 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E601 | Decision to refuse application |