KR930006816A - 반도체 장치 및 그 제조방법 - Google Patents
반도체 장치 및 그 제조방법 Download PDFInfo
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- KR930006816A KR930006816A KR1019920017298A KR920017298A KR930006816A KR 930006816 A KR930006816 A KR 930006816A KR 1019920017298 A KR1019920017298 A KR 1019920017298A KR 920017298 A KR920017298 A KR 920017298A KR 930006816 A KR930006816 A KR 930006816A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K7/00—Constructional details common to different types of electric apparatus
- H05K7/02—Arrangements of circuit components or wiring on supporting structure
- H05K7/023—Stackable modules
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Dispersion Chemistry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
본 발명은, 회로기판상의 반도체 소자가 집적회로 소자와 파위 소자가 혼재된 것이어도 고밀도로 실장할 수 있도록 된 구조의 반도체 장치에 관한 것이다.
본 발명은, 복수의 회로기판(4)을 이용하여 각각 그 외주를 에워싸는 틀(8)을 부착시키고, 각 틀(8)에는 각 회로기판(4)에 전기적으로 접속된 접속단자(71, 72)가 부착되어 있기 때문에 제1를(81)과 제2를(82)을 겹쳐 쌓아 각각의 접속단자를 접속시키면 회로기판은 상호 전기적으로 접속하여 고밀도 실장된 반도체 장치가 형성된다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에 따른 반도체 장치의 단면도,
제2도는 본 발명의 제1실시예에 따른 반도체 장치의 부분 단면도,
제3도는 본 발명의 제1실시예에 따른 반도체 장치의 제조공정 단면도,
제4도는 본 발명의 제1실시예에 따른 반도체 장치의 제조공정 단면도.
Claims (10)
- 제1틀(81)이 그 주위에 부착된 제1회로기판(4)과, 이 제1회로기판(4)에 적충되면서 제2틀(82)이 그 주위에 부차된 제2회로기판(4), 상기 제1및 제2회로기판(4)에 각각 탑재된반도체 소자(5, 9), 상기 제1를(81)에 형성되면서 상기 제1회기판(4)과 전기적으로 접속된 제1전기적 접속수단(72)및, 상기 제2를(82)에 형성되면서 상기 제2회로기판(4)과 전기적으로 접속된 제2전기적 접속수단(71)을 구비하고, 상기 제1전기적 접속 수단(72)고 상기 제2전기적 접속수단(71)을 전기적으로 접속함으로써 상기 제1및 제2회로기판(4)을 상호 전기적으로 접속되도록 된 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서, 상기 제1전기적 접속수단(72)은 상기 제1를(81)로 부터 돌출된 제1접속단자로 이루어지고, 상기 제2전기적 접속수단(71)은 상기 제2를(82)에 형성된 흠속에 배치된 제2접속단자로 이루어지며, 상기 제1접속단자가 상기 흠속의 제2접속단자와 접촉되어 제1및 제2회로기판(4, 4)이 전기적으로 접속되도록 된 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서, 상기 제1전기적 접속수단(72)은 상기 제1를 (81)로부터 돌출된 제1접속단자와 상기 제1를(81)의 표면상에 상기 제1접속단자를 에워싸도록 형성된 도전층으로 이루어지고, 상기 제2전기적 접속수단(71)은 상기 제2를(82)의 표면상에 형성되면서 접촉구멍을 갖춘 제2접속단자로 이루어지며, 상기 제1접속단자는 이 접촉구멍을 통해 상기 제2를(82)에 형성된 흠에 삽입됨으로써 상기 도전층 및 제1접속단자에 접촉 되도록 된 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서, 상기 제1회로기판(4)에는 상기 반도체 소자로서 파워 소자가 탑재되어 있거나 또는 집적회로 소자와 파워 소자가 혼재되어 있고, 상기 제2회로기판(4)에는 상기 반도체 소자로서 집적회로소자가 탑재되어 있거나 또는 집적회로소자와 파워소자가 혼재되어 있는 것을 특징으로 하는 반도체 장치.
- 제4항에 있어서, 상기 파워 소자를 탑재한 상기 제1및 제2호르가판(4)의 어느 한쪽 또는 양쪽의 반도체 소자가 탑재되어 있는 면과는 반대의 면에 방열장치(3)를 부착시킨 것을 특징으로 하는 반도체.
- 제5항에 있어서, 상기 방열장치(3)는 그 회로기판에 부착되어 있는 틀의 임의의 변의 내측벽 및 그 다른 변의 저면에 접합되어 있는 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서, 상기 제2회로기판(4)에는 외주에 제3를(83)이 부착된 제3회로기판(4)이 적층되고, 이 제3를(83)에는 상기 제3회로기판(4)과 전기적으로 접속된 제3전기적 접속수단(72)이 설치되어 있으며, 상기 제2전기적 접속수단(71)과 상기 제3전기적 접속수단(72)을 전기적으로 접속함으로써 상기 제2및 제3회로기판(4, 4)을 상호 전기적으로 접속하도록 된 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서, 상기 제1틀(81)에는 그 외주에 돌기부(86)를 형성하고, 상기 제2를(82)에는 그 외주에 절결부(87)를 형성하며, 상기 돌기부(86)및 절결부(87)를 끼워 맞추어서 상기 제2를(82)을 제1를(81)에 고정시키도록 된 것을 특징으로 하는 반도체 장치.
- 복수의 리드를 소정의 간격으로 금형내에 배치하는 공정과, 상기 금형에 절연을을 충전하여 경화시켜 상기 리드가 부착되는 틀을 형성하는 공정, 상기 리드를 가공하여 상기 틀에 전기적 접속수단을 부착시키는 공정, 상기 틀에 회로기판을 부착시키는 공정, 상기 회로기판에 집적회로소자 또는 그 양자로 이루어진 반도체 소자를 탑재하는 공정 및, 상기 회로기판과 상기 전기적 접속수단을 전기적으로 접속하는 공정을 구비하여 이루어진 것을 특징으로 하는 반도체 장치.
- 제9항에 있어서, 상기 리드를 가공하여 상기 틀내에 전기적 접속수단을 부착시키는 공정에 있어서, 상기 리드를 가공할 때에 외부리드도 형성하도록 된 것을 특징으로 하는 반도체 장치의 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP91-274764 | 1991-09-26 | ||
JP3274764A JP2642548B2 (ja) | 1991-09-26 | 1991-09-26 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR930006816A true KR930006816A (ko) | 1993-04-21 |
KR960000711B1 KR960000711B1 (ko) | 1996-01-11 |
Family
ID=17546253
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920017298A KR960000711B1 (ko) | 1991-09-26 | 1992-09-23 | 반도체장치 및 그 제조방법 |
Country Status (3)
Country | Link |
---|---|
US (1) | US5295044A (ko) |
JP (1) | JP2642548B2 (ko) |
KR (1) | KR960000711B1 (ko) |
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US4356532A (en) * | 1980-07-18 | 1982-10-26 | Thomas & Betts Corporation | Electronic package and accessory component assembly |
DE8808743U1 (de) * | 1988-07-07 | 1988-09-01 | Siemens AG, 1000 Berlin und 8000 München | Elektronik-Baugruppe |
EP0353443B1 (de) * | 1988-08-03 | 1993-01-27 | Mannesmann Kienzle GmbH (HR B1220) | Gehäuse für ein elektronisches Gerät |
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JPH03190190A (ja) * | 1989-12-19 | 1991-08-20 | Toshiba Corp | 混成集積回路装置 |
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US5172303A (en) * | 1990-11-23 | 1992-12-15 | Motorola, Inc. | Electronic component assembly |
KR920018913A (ko) * | 1991-03-30 | 1992-10-22 | 김광호 | 반도체 장치 및 그의 제조 방법 |
-
1991
- 1991-09-26 JP JP3274764A patent/JP2642548B2/ja not_active Expired - Fee Related
-
1992
- 1992-09-23 KR KR1019920017298A patent/KR960000711B1/ko not_active IP Right Cessation
- 1992-09-25 US US07/950,899 patent/US5295044A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR960000711B1 (ko) | 1996-01-11 |
US5295044A (en) | 1994-03-15 |
JP2642548B2 (ja) | 1997-08-20 |
JPH0590482A (ja) | 1993-04-09 |
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