GB2379330A - Package for electronic components and method for forming a package for electronic components - Google Patents

Package for electronic components and method for forming a package for electronic components Download PDF

Info

Publication number
GB2379330A
GB2379330A GB0121002A GB0121002A GB2379330A GB 2379330 A GB2379330 A GB 2379330A GB 0121002 A GB0121002 A GB 0121002A GB 0121002 A GB0121002 A GB 0121002A GB 2379330 A GB2379330 A GB 2379330A
Authority
GB
United Kingdom
Prior art keywords
substrate
conductive
package
substrates
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB0121002A
Other versions
GB0121002D0 (en
Inventor
Torsten Hauck
Christina Brigitte Bohm
Anton Kolbeck
Cynthia Lee Trigas
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Priority to GB0121002A priority Critical patent/GB2379330A/en
Publication of GB0121002D0 publication Critical patent/GB0121002D0/en
Priority to PCT/EP2002/006071 priority patent/WO2003021678A1/en
Priority to TW091113631A priority patent/TW550713B/en
Publication of GB2379330A publication Critical patent/GB2379330A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/144Stacked arrangements of planar printed circuit boards
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/162Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/165Containers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/119Details of rigid insulating substrates therefor, e.g. three-dimensional details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/162Disposition
    • H01L2924/1627Disposition stacked type assemblies, e.g. stacked multi-cavities
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/0999Circuit printed on or in housing, e.g. housing as PCB; Circuit printed on the case of a component; PCB affixed to housing
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2018Presence of a frame in a printed circuit or printed circuit assembly

Abstract

The invention relates to a package 2 for electronic components 8, 10 comprising at least two substrates 4, 6. Each substrate supports an electronic component 8, 10. External connectors 34 provide external connection to the electronic components 8, 10. A non-conductive frame 12 supports the at least two substrates 4, 6 in a stacked arrangement, and the external connectors 34. Conductive lines 36, 38 extend over the non-conductive frame 12 for electrically coupling the electronic components 8, 10 to the external connectors 34.

Description

<Desc/Clms Page number 1>
PACKAGE FOR ELECTRONIC COMPONENTS AND METHOD FOR FORMING A PACKAGE FOR ELECTRONIC COMPONENTS Field of the Invention This invention relates to packages for electronic components and a method for forming packages for electronic components. More particularly, this invention relates to packages comprising at least two substrates in a stacked arrangement.
Background of the Invention Electronic components are contained in packaging to support and protect the components, to provide heat dissipation and to provide external mechanical and electrical connectors to the components.
Typically, a package comprises a single substrate on which is mounted the electronic components and a lead frame having leads which form the external connectors to the components. Contact pads are formed on the substrate and the lead frame is attached to the contact pads using solder. Conductive lines extend over the substrate for providing electrical connections between the components and/or the lead frame. The type of connection used to connect the conductive lines to the components depend on the components. For example, for surface mount devices (SMD), contact pads on the devices are soldered directly to contact areas of the conductive lines. Another connection technique is wire bonding.
With the drive for electronic devices with more functionality, there is a need to increase the number of components in a package. In order to increase the number of components in this conventional type of packaging, the size or footprint of the package must be increased. This is due to the increase in the number of components plus also the increase in conductive lines on the substrate needed for the additional components. Since the conductive lines are formed on one surface of the substrate, the conductive lines cannot cross-over each other and so preparing the design layout for the components and conductive lines becomes more challenging as the component count increases.
<Desc/Clms Page number 2>
US patent no. 6,020, 629 discloses a stacked semiconductor package arrangement in which substrates are stacked on top of one another. Each of the substrates has a single semiconductor die mounted on a first side of the substrate. Wire bonds connect the semiconductor die to contact pads on the first side of the substrate. Connection is made between the contact pads and an external contact on a second opposing side of the substrate via a hole in the substrate containing metal. The substrates are connected together by bonding the external contact of one substrate with the contact pad of an adjacent stacked substrate.
The stacked arrangement disclosed in this US patent provides a package in which the number of components can be increased without increasing the footprint of the package but the fabrication of the single substrates and the interconnection between the substrates is complicated and expensive. In addition, external mechanical and electrical connectors to the components are not integrated into the stack which means additional steps are required to connect the stack to an application, for example a motor. Furthermore, such an arrangement would not be suitable for power devices since the described arrangement does not provide for sufficient heat dissipation.
There is therefore a need for an improved package which comprises multiple electronic components with increased packaging density and external mechanical and electrical connection.
Summary of the Invention In accordance with a first aspect of the present invention there is provided a package for electronic components as recited in claim 1 of the accompanying claims.
In accordance with a second aspect of the present invention there is provided a method for forming a package for electronic components as recited in claim 11 of the accompanying claims.
Brief Description of the Drawings
<Desc/Clms Page number 3>
A package for electronic components and a method for forming a package for electronic components in accordance with a preferred embodiment of the invention will now be described with reference to the accompanying drawings in which: FIG. 1 is a cross-sectional schematic diagram of a package in accordance with the present invention; FIG. 2 is a schematic plan diagram of a non-conductive frame for the package of FIG. 1; FIG. 3 is a cross-sectional schematic diagram of part of the frame of FIG.
2 showing possible different arrangements of the conductive lines formed on the frame; and FIG. 4 is a schematic plan view of the different assembly steps of the package of FIG. 1.
Detailed Description of the Drawings Referring firstly to FIG. 1, a package 2 in accordance with a preferred embodiment of the invention comprises a first substrate 4 and a second substrate 6 supported by a non-conductive frame 12 in a stacked arrangement. The first substrate 4 has a first side 16 and second 18 opposing side and supports one or more electronic components 8 on at least one of the first 16 and second 18 sides.
The second substrate 6 has a first side 20 and a second 22 opposing side and supports one or more electronic components 10 on at least one of the first 20 and second 22 sides. Double-sided substrates on which components are mounted on both sides of the substrate are well known.
Substrates 4 and 6 may be the same type of substrate (e. g. single or double-sided printed circuit boards) and formed from the same material or two different types and/or made from different material. In the example shown in FIG.
1, the components 8 are low power devices such as logic devices and discrete devices which means that the first substrate can be a double-sided substrate comprising a glass filled resin such as an epoxy glass (FR-4). The components 10 are power devices so the second substrate 6 is a single-sided substrate comprising a thermally enhanced material such as ceramic or an Insulated Metal Substrate. Since the second substrate 6 is a single-sided substrate, a heat sink
<Desc/Clms Page number 4>
14 may be attached by thermally conductive interface material, such as an adhesive or paste, to the second side 22 of the second substrate 6 in order to enhance heat dissipation.
An advantage of selecting the type and material of the substrate according to the components to be mounted on the substrate is that an optimum structure can be obtained from a size (i. e. double-sided means more components can be included or components requiring large interconnect count can be more easily accommodated), cost (i. e. cheaper substrates can be used for the low power devices) and performance (i. e. enhanced thermal dissipation for power devices) perspective. The components may be any type of electronic component, for example, active semiconductor devices such as transistors, microcontrollers, Digital Signal Processors (DSPs) etc. and/or passive devices such as discrete resistors, capacitors or inductors.
The components 8 and 10 shown in FIG. 1 are SMDs and are mounted to die pads (not shown) on the substrates 4 and 6 by flip-chip or wire bonding techniques as is well known in the art. It will be appreciated that the invention may be used for any other type of devices such as THDs (Through-Hole Devices) or the like.
The first substrate 4 has conductive contact pads 24 formed on the second side 18 of the first substrate 4. The second substrate 6 has conductive contact pads 26 formed on the first side 20 of the second substrate 6. The conductive contact pads 24 and 26 are electrically coupled to the components 8 and 10 via substrate conductive lines extending over the substrates 4 and 6. In FIG. 1, only the substrate conductive lines 28 coupled between the conductive contact pads 26 and the components 10 are shown.
Although the conductive contact pads 24 and 26 are shown in FIG. 1 as formed on the second 18 and first 20 sides of the first 4 and second 6 substrates respectively, the conductive contact pads 24 and 26 may also be formed on both the first and second sides of the first 4 and second 6 substrates or on the first 16 and second 22 sides of the first 4 and second 6 substrates respectively.
The components 8 on the first side 16 of the first substrate 4 may be coupled to the conductive contact pads 24 on the second side 18 by way of vias (not shown) in the first substrate 4 and substrate conductive lines on the second
<Desc/Clms Page number 5>
side 18 of the first substrate 4 and/or by having conductive contact pads on the first side 18 of the substrate 4.
The shape of the non-conductive frame 12 will depend on the position of the conductive contact pads 24 and 26 as will become apparent below.
Referring now also to FIG. 2, the non-conductive frame 12, which is preferably formed from molded plastic material by injection molding techniques, is arranged to provide a substrate cavity 30 in which the first 4 and second 6 substrates are supported in a stacked arrangement. The non-conductive frame 12 comprises a wall 13 that encloses the substrate cavity 30. The non- conductive frame 12 has a plurality of connector cavities 32 extending from external to the package 2 through the non-conductive frame 12 towards the substrate cavity 30. In FIG. 1, the connector cavities 32 are shown extending right into the substrate cavity 30 so as to provide holes through the nonconductive frame 12 but the connector cavities 32 need not extend right into the substrate cavity 30. External connectors 34 extend into the connector cavities 32. Although not shown in FIG. 1, the external connectors 34 may extend right into the substrate cavity 30.
FIG. 2 shows a number of external connectors 34 on two sides of the nonconductive frame 12. It will however be appreciated that there may be two external connectors 34 on one side only of the non-conductive frame 12 or a number of external connectors 34 on three or all sides of the non-conductive frame 12. The arrangement shown in FIGs. 1 and 2 is for illustrative purposes only and not intended to be limiting.
The non-conductive frame 12 is shaped so that portions 15 of the frame 12 extend partly (i. e. a short distance) across the second 18 and first 20 sides of the first 4 and second 6 substrates so as to be adjacent and in a plane parallel to the conductive contact pads 24 and 26.
The package 2 further comprises first conductive lines 36 extending over the non-conductive frame 12 into the connector cavities 32 and over the portions 15 for electrically coupling the conductive contact pads 24 of the first substrate 4 to the external connectors 34 and second conductive lines 38 extending over the non-conductive frame 12 into the connector cavities 32 and over the portions 15 for electrically coupling the conductive contact pads 26 of the second substrate 6
<Desc/Clms Page number 6>
to the external connectors 34. Solder or conductive adhesive 50 attaches the conductive lines 36 and 38 to the respective conductive contact pads 24 and 26.
The first 36 and second 38 conductive lines may extend over the nonconductive frame 12 to contact the same external connectors 34 as shown in FIGs. 1 and 2 and example 42 in FIG. 3. In addition or alternatively, the first 36 and second 38 conductive lines may be staggered so that the conductive contact pads 24 and 26 are coupled to different external connectors 34, as shown in examples 44 and 46 in FIG. 3. In addition, the first 36 and second 38 conductive lines may extend round the non-conductive frame 12 to interconnect the conductive contact pads 24 of the first substrate 4 with the conductive contact pads 26 of the second substrate 6, as shown in example 48 in FIG. 3.
As discussed above, the conductive contact pads 24 and 26 may also or instead be on the other sides of the first 4 and second 6 substrates respectively to those shown in FIG. 1 (i. e. on sides 16 and 22 respectively). In these cases, the non-conductive frame 12 would be shaped so that the non-conductive frame 12 has portions that extend partly across the first side 16 of the first substrate 4 and/or the second side 22 of the second substrate 6 to enable the conductive lines 36 and 38 to be adjacent and to make contact with the conductive contact pads 24 and 26, respectively.
Preferably, the conductive pads 24 and 26, the substrate conductive lines 28 and the first 36, second 38 and third 40 conductive lines are formed from metal.
Since the connections to the external connectors 34 and/or the other substrates 4 and 6 are made via the conductive lines 36 and 38 formed over the non-conductive frame 12, the task of doing the design layout can be very much simplified. In other words, simply adding additional conductive lines over the non-conductive frame 12 can solve routing problems and in particular cross-over problems. A further advantage of this arrangement is that standard devices can be used and the functionality changed depending on the application simply be changing the arrangement of the conductive lines on the non-conductive frame 12.
In the preferred embodiment, a lid 52 is provided. The lid 52 and heat sink 14 provide a completely sealed package.
<Desc/Clms Page number 7>
A method for forming the package 2 in accordance with a preferred embodiment of the present invention will now be described with reference to FIGs. 1-3 and FIG. 4 which shows an exploded view of the different assembly steps of the preferred embodiment.
The substrates 4 and 6 are provided and the electronic components 8 and 10 are mounted on the substrates 4 and 6 respectively and the conductive contact pads 24 and 26 formed using conventional printed circuit board materials and assembly processes. In the preferred embodiment, the first substrate 4 is a double-sided FR-4 substrate and the components 8 are mounted on both sides 16 and 18 using flip-chip or wire-bonding techniques. The second substrate 6 is a single-sided thermally enhanced substrate for high power components 10 which are mounted using standard flip-chip or wire-bonding techniques.
The assembled substrates are then electrically tested.
The non-conductive frame 12 with external connectors 34 is fabricated.
Preferably, the non-conductive frame 12 is made of plastic and is molded round a metal lead frame (not shown) comprising the external connectors 34. The nonconductive lead frame 12 is molded to the shape shown in FIG. 2 with the substrate cavity 30, portions 15 and the connector cavities 32 containing the external connectors 34. Parts of the lead frame are then removed to leave the external connectors 34 in the connector cavities 32. Metal is then deposited on the non-conductive frame 12 to form the network of conductive lines 36 and 38.
Such a 3D-molded interconnect device (3D-MID) is well known in the art. For example, an article by Klaus Feldmann et al entitled'MID in the Automotive Industry-Potentials, Benefits and Applications (1998IEEE/CPMT Berlin International Electronics Manufacturing Technology Symposium pages 76-81 provides an example of MID technology. Alternatively, parts of the lead frame may be removed so that the external connectors 34 extend into the substrate cavity 30 in which case the end portions of the connectors in the substrate cavity 30 are formed round the portions 15 of the frame 12 to provide the conductive lines 36,38.
An alternative method of fabricating the non-conductive lead frame 12 involves molding the non-conductive frame 12 to the shape shown in FIG. 2 with the connector cavities 32, substrate cavity 30 and portions 15, forming the
<Desc/Clms Page number 8>
external connectors 34 separately and then press fitting the external connectors 34 into the connector cavities 32.
Solder or conductive adhesive 50 is then deposited on the conductive contact pads 24 and 26 and/or areas 35 on the conductive lines 36 and 38, which areas are for contacting the conductive contact pads 24 and 26. The assembled substrates 4 and 6 are then mounted on the non-conductive frame 12 such that the conductive contact pads 24 and 26 are adjacent the areas 35 of the conductive lines 36 and 38 with the solder or conductive adhesive 50 in between.
The partially assembled package then undergoes a solder reflow process or an adhesive curing process. This could be a two-step process, one for each substrate, or a one-step process in which both substrates are soldered to the conductive lines at the same time.
A lid 52 and metal heat sink 14 may then be attached to the package and the whole package sealed.
The substrate cavity 30 and the cavity 54 formed above the first substrate 4 may be filled or not. For example, the cavity 30 may be filled with air, an appropriate gas to detect leaks, or a potting compound to provide a seal and protection against environmental impacts.
The package 2 in accordance with the invention may be simplified based on the requirements of a given application. For example, single-sided substrates may be used for the first 4 and second 6 substrates and the lid 52 and heat sink 14 removed. Instead of using lids and/or heat sinks, sealing can be established by filling the gap between the substrates 4 and 6 and the non-conductive frame 12 with adhesive material. Another example is electromagnetic shielding can be provided with single-sided substrates by internal or backside metallisation layers.
Such a package is useful for wireless communication and/or automotive applications.
The invention has been described with reference to a package comprising two substrates. The invention may however apply to two or more substrates stacked in the substrate cavity 30.
In summary, the present invention provides a package having multiple electronic components with increased packaging density by way of stacked substrates and an integrated external mechanical and electrical connection.
Having a non-conductive frame that supports the stacked substrates plus
<Desc/Clms Page number 9>
supports the external connectors and conductive lines for coupling the components on the substrates to the external connectors is a simple and cost effective way to provide external connection without the need for additional substrates.
In addition, the ability to be able to add conductive lines to the frame and hence connections between the external connectors and the components provides a flexible package which enables a designer to more easily change components according to functional requirements. For example, with the present invention the expensive power board on say the second substrate can be kept the same and become a standard for many different applications and only the logic on the first less expensive substrate needs to be changed according to the required application.
The present invention further provides improved testability. For standard packages, when one component fails the whole package has to be thrown away whereas with the present invention, if a component fails only the substrate with the failed component needs to be changed. In addition, since several substrates are used, the components on the different substrates can be more easily tested separately.
As discussed above, the stacked arrangement enables different substrates to be used to optimise performance according to the type of component.

Claims (15)

  1. Claims 1. A package for electronic components comprising: at least two substrates, each substrate for supporting an electronic component; external connectors for providing external connection to the electronic components; a non-conductive frame for supporting the at least two substrates in a stacked arrangement, and the external connectors; and conductive lines which extend over the non-conductive frame for electrically coupling the electronic components to the external connectors.
  2. 2. A package as claimed in claim 1 wherein the non-conductive frame comprises a wall surrounding a substrate cavity and connector cavities extending from external to the package through the wall of the non-conductive frame towards the substrate cavity, the non-conductive frame supporting the at least two substrates in the substrate cavity and the external connectors in the connector cavities.
  3. 3. A package comprising: a first substrate for supporting an electronic component, the first substrate having a conductive contact pad electrically coupled to the first electronic component; a second substrate for supporting a second electronic component, the second substrate having a conductive contact pad electrically coupled to the electronic component; a non-conductive frame arranged to form a substrate cavity, the nonconductive frame supporting the first and second substrates in a stacked arrangement in the substrate cavity, the non-conductive frame further having a connector cavities extending from external to the package through the nonconductive frame towards the substrate cavity; external connectors extending into respective connector cavities;
    <Desc/Clms Page number 11>
    a first conductive line extending over the non-conductive frame and into a connector cavity for electrically coupling the conductive contact pad of the first substrate to an external connector; and a second conductive line extending over the non-conductive frame and into a connector cavity for electrically coupling the conductive contact pad of the second substrate to an external connector.
  4. 4. The package as claimed in claim 3 wherein the conductive contact pads of the first and second substrates are coupled to the same external connector or different external connectors via the respective first and second conductive lines.
  5. 5. The package as claimed in claim 3 or 4 further comprising a plurality of conductive contact pads on the first and second substrates and a third conductive line extending over the non-conductive frame for electrically coupling a conductive contact pad of the first substrate to a conductive contact pad of the second substrate.
  6. 6. The package as claimed in claim 3,4 or 5 wherein the first substrate comprises first and second opposing sides and the second substrate comprises first and second opposing sides, the first and second substrates being stacked in the substrate cavity such that the second side of the first substrate faces the first side of the second substrate, and wherein conductive contact pads are provided on the second side of the first substrate and the first side of the second substrate.
  7. 7. The package as claimed in claim 6 wherein the electronic component is mounted on the first side of the second substrate and the package further comprises a heat sink coupled to the second side of the second substrate.
  8. 8. The package as claimed in claim 3,4, 5,6 or 7 further comprising a plurality of electronic components mounted on the first and second substrates.
  9. 9. The package as claimed in claim 6 further comprising a plurality of electronic components mounted on the first and second sides of one or both of the first substrate and the second substrates.
    <Desc/Clms Page number 12>
  10. 10. The package as claimed in claim 3,4, 5,6 or 7 wherein the substrate cavity is filled with one of the following : air, helium, and potting compound.
  11. 11. A method of forming a package comprising the steps of: providing at least two substrates; mounting an electronic component on each substrate; providing a non-conductive frame for supporting the at least two substrates in a stacked arrangement, and external connectors for providing external connection to the electronic components; and forming conductive lines on the non-conductive frame which extend over the non-conductive frame for electrically coupling the electronic components to the external connectors.
  12. 12. A method as claimed in claim 11 wherein the providing a non-conductive frame step comprises: providing a lead frame comprising the external connectors; forming the non-conductive frame round the lead frame, the nonconductive frame having a wall surrounding a substrate cavity and connector cavities extending from external to the package through the wall of the nonconductive frame towards the substrate cavity; removing the lead frame so as to leave external connectors mounted in the non-conductive frame such that the external connectors extend into the connector cavities; and mounting the at least two substrates on the non-conductive frame such that the substrates extend across the substrate cavity.
  13. 13. A method as claimed in claim 11 wherein the providing a non-conductive frame step comprises: providing external connectors; forming the non-conductive frame having a wall surrounding a substrate cavity and connector cavities extending from external to the package through the non-conductive frame towards the substrate cavity;
    <Desc/Clms Page number 13>
    mounting the external connectors in the frame such that the external connectors extend into the connector cavities; and mounting the at least two substrates on the non-conductive frame such that the substrates extend across the substrate cavity.
  14. 14. A package substantially as hereinbefore described with reference to the accompanying drawings.
  15. 15. A method of forming a package substantially as hereinbefore described with reference to the accompanying drawings.
GB0121002A 2001-08-29 2001-08-29 Package for electronic components and method for forming a package for electronic components Withdrawn GB2379330A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
GB0121002A GB2379330A (en) 2001-08-29 2001-08-29 Package for electronic components and method for forming a package for electronic components
PCT/EP2002/006071 WO2003021678A1 (en) 2001-08-29 2002-06-03 Package for electronic components and method for forming a package for electronic components
TW091113631A TW550713B (en) 2001-08-29 2002-06-21 Package for electronic components and method for forming a package for electronic components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0121002A GB2379330A (en) 2001-08-29 2001-08-29 Package for electronic components and method for forming a package for electronic components

Publications (2)

Publication Number Publication Date
GB0121002D0 GB0121002D0 (en) 2001-10-24
GB2379330A true GB2379330A (en) 2003-03-05

Family

ID=9921207

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0121002A Withdrawn GB2379330A (en) 2001-08-29 2001-08-29 Package for electronic components and method for forming a package for electronic components

Country Status (3)

Country Link
GB (1) GB2379330A (en)
TW (1) TW550713B (en)
WO (1) WO2003021678A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL1035663C2 (en) * 2008-07-04 2010-01-05 Thales Nederland Bv A method for manufacturing a three-dimensional multi-layered (multi-layer) interconnection facility.
US10121742B2 (en) * 2017-03-15 2018-11-06 Amkor Technology, Inc. Method of forming a packaged semiconductor device using ganged conductive connective assembly and structure
TWI723816B (en) * 2020-03-23 2021-04-01 綠達光電股份有限公司 Power integrated circuit for motor with heat dissipation structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0560502A2 (en) * 1992-03-09 1993-09-15 Matsushita Electric Industrial Co., Ltd. Electronic circuit device and manufacturing method thereof
US5295044A (en) * 1991-09-26 1994-03-15 Kabushiki Kaisah Toshiba Semiconductor device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR940006427Y1 (en) * 1991-04-12 1994-09-24 윤광렬 Magnifying lens
DE69227066T2 (en) * 1991-05-31 1999-06-10 Denso Corp Electronic device
GB9304956D0 (en) * 1993-03-11 1993-04-28 British Aerospace Integrated circuits
US5880403A (en) * 1994-04-01 1999-03-09 Space Electronics, Inc. Radiation shielding of three dimensional multi-chip modules
JP3721848B2 (en) * 1999-04-23 2005-11-30 松下電工株式会社 MID board inspection method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5295044A (en) * 1991-09-26 1994-03-15 Kabushiki Kaisah Toshiba Semiconductor device
EP0560502A2 (en) * 1992-03-09 1993-09-15 Matsushita Electric Industrial Co., Ltd. Electronic circuit device and manufacturing method thereof

Also Published As

Publication number Publication date
WO2003021678A1 (en) 2003-03-13
TW550713B (en) 2003-09-01
GB0121002D0 (en) 2001-10-24

Similar Documents

Publication Publication Date Title
US10297573B2 (en) Three-dimensional package structure and the method to fabricate thereof
US5705851A (en) Thermal ball lead integrated package
EP3499560B1 (en) Semiconductor module and method for producing the same
US6057601A (en) Heat spreader with a placement recess and bottom saw-teeth for connection to ground planes on a thin two-sided single-core BGA substrate
US7145084B1 (en) Radiation shielded module and method of shielding microelectronic device
US4819041A (en) Surface mounted integrated circuit chip package and method for making same
JP2910670B2 (en) Semiconductor mounting structure
US20040109292A1 (en) Reversible heat sink packaging assembly for an integrated circuit
TWI670804B (en) Semiconductor device
CN109244045B (en) Miniaturized metal tube shell packaging structure of thick film substrate
KR20010034154A (en) Semiconductor component with several substrate layers and at least one semiconductor chip and method for producing a semiconductor component
WO2005104231A2 (en) Multi-substrate circuit assembly
KR100647090B1 (en) Semiconductor component with several semiconductor chips
KR20060112230A (en) Carrying structure of electronic components
KR20050021905A (en) Package for a semiconductor device
JPH0730059A (en) Multichip module
GB2379330A (en) Package for electronic components and method for forming a package for electronic components
KR20040063784A (en) Semiconductor apparatus
JP2780424B2 (en) Hybrid integrated circuit
JPH04206658A (en) Hermetic seal type electric circuit device
CN113394174A (en) System and method for device packaging
KR20080068299A (en) Semiconductor module and manufacturing method thereof
GB2380613A (en) Package for electronic components and method for forming such a package
KR950028068A (en) Multilayer semiconductor package and manufacturing method thereof
KR200283907Y1 (en) Ball Grid Array Package Stacked Semiconductor Device

Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)