KR940020192A - 다중 전력 공급원 분리기능을 갖는 완전 스윙 전력 강하 버퍼회로 - Google Patents

다중 전력 공급원 분리기능을 갖는 완전 스윙 전력 강하 버퍼회로 Download PDF

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KR940020192A
KR940020192A KR1019940002320A KR19940002320A KR940020192A KR 940020192 A KR940020192 A KR 940020192A KR 1019940002320 A KR1019940002320 A KR 1019940002320A KR 19940002320 A KR19940002320 A KR 19940002320A KR 940020192 A KR940020192 A KR 940020192A
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South Korea
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well
output
power rail
vcc
transistor
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KR1019940002320A
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KR100298927B1 (ko
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에이치. 라르손 데이비드
비. 부머 제임스
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낸시 루크 루저스
내쇼날 세미컨덕터 코포레이션
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0218—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of field effect structures
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H03K19/09429—Multistate logic one of the states being the high impedance or floating state

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

완전 스윙 CMOS 출력 버퍼회로(20, 30, 40, 50)는 3.3V 표준 및 5V 표준 서브회로와 같은 양립가능하지 않은 전력공급원 회로를 분리시키고, 공통 외부버스와 침묵 또는 전력강하 버퍼회로의 전력공급원 레일을 분리시킨다. 풀업출력 트랜지스터(PMOSI)는 P형 캐리어 반도체 재료의 기판(PSUB)내에 형성된 N형 캐리어 반도체 재료의 웰(N웰)내에 제조된다. P채널 N웰 분리스위치 트랜지스터(PW1)는 상기 월(N웰) 및 고전위 전력 레일(VCC)사이에 연결된 주전류 경로 및 거의 동상으로 동작하도록 풀업 출력 트랜지스터(PMOS1)의 제어 게이트 노드에 연결된 게이트 노드를 갖는다. N웰 분리 스위치 트랜지스터(PW1)는 고전위 전력 레일(VCC)과 풀업출력 트랜지스터(PMOS1) 웰(N웰)을 분리시킨다. N채널 제어노드 분리 트랜지스터(N1)는 전력 강하시 출력 트랜지스터(PMDS1, NMOS1)의 제어 노드를 서로 분리시키도록 고전위 전력 레일(VCC)에 연결된 제어 노드를 지닌다. P채널 피드백 턴오프 트랜지스터(PPI)는 출력(VOUT)에 발생되는 보다 높은 전위 레벨 신호에 응답하여 출력 트랜지스터(PMOs1, NMOS1)를 턴오프시키도록 고전위 전력 제일(VCC)에 연결된 제어 노드를 지닌다. 지연 방전 회로(DDC)는 전력 강하시 고전위 전력레일(VCC)로부터 과도전하를 방전시킨다.

Description

다중 전력 공급원 분리기능을 갖는 완전 스윙 전력 강하 버퍼회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 신규한 구성요소(PW1, PP1, N1, SD2)를 합체하는 본 발명에 따른 신규한 출력 버퍼회로에 대한 개략적인 회로 다이어그램.

Claims (1)

  1. 고 및 저전위 레벨의 출력 신호를 공급하는 출력(VOUT) 및 상기 출력(VOUT)및 정반대인 고(VCC) 및 저(GND) 전위 전력 레일의 선택된 전력 레일(VCC)사이에 연결된 주전류 경로를 갖는 선택된 출력 트랜지스터(PMOS1)를 구비하는 버퍼회로(20, 30, 40, 50)로서, 상기 선택된 출력 트랜지스터(PMOS1)는 상기 선택된 출력 트랜지스터 주전류 경로의 도통상태를 제어하도록 상기 버퍼회로내에 연결된 제어 노드를 지니며, 제2형태의 캐리어 반도체 재료의 기판(PSUB) 내에 형성된 제1형태의 캐리어 반도체 재료의 웰(N웰)내에 제조되고, 상기 웰은 선택된 전력 레일(VCC)에 연결되어 있으며 상기 기판(PSUB)은 정반대 전력레일(GND)에 연결되어 있는 것을 특징으로 하는 버퍼회로에 있어서, 상기 선택된 전력 레일(VCC) 및 상기 출력 트랜지스터(PMOS1)의 웰(N웰) 사이에 연결된 주전류 경로를 갖는 웰 분리 스위치 트랜지스터(PW1)로서, 상기 선택된 출력 트랜지스터(PMOS1)의 제어 노드에 연결된 제어 노드를 지녀서 상기 선택된 출력트랜지스터(PMOS1)와 거의 동상으로 웰 분리 스위치 트랜지스터(PW1)의 도통상태를 제어함으로써 상기 출력 트랜지스터(PMOS1)가 도통상태에 있지 않을 경우 상기 선택된 전력 레일(VCC)과 상기 출력 트랜지스터(PMOS1) 웰(N웰)을 분리시키는 것을 특징으로 하는 웰 분리 스위치 트랜지스터(PW1)를 포함하는 개선된 버퍼회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940002320A 1993-02-10 1994-02-08 다중 전원 분리를 지니는 풀 스윙 파워 다운 버퍼 회로 KR100298927B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/016,009 US5338978A (en) 1993-02-10 1993-02-10 Full swing power down buffer circuit with multiple power supply isolation
US93-08/106,009 1993-02-10
US93-08/016,009 1993-02-10

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KR940020192A true KR940020192A (ko) 1994-09-15
KR100298927B1 KR100298927B1 (ko) 2001-10-22

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US (1) US5338978A (ko)
JP (1) JP3109641B2 (ko)
KR (1) KR100298927B1 (ko)
DE (1) DE4404132C2 (ko)

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Publication number Publication date
DE4404132C2 (de) 2003-03-06
DE4404132A1 (de) 1994-08-11
JPH077410A (ja) 1995-01-10
US5338978A (en) 1994-08-16
JP3109641B2 (ja) 2000-11-20
KR100298927B1 (ko) 2001-10-22

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