KR940010194A - 반도체장치의 배선층 형성방법 - Google Patents

반도체장치의 배선층 형성방법 Download PDF

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Publication number
KR940010194A
KR940010194A KR1019920018178A KR920018178A KR940010194A KR 940010194 A KR940010194 A KR 940010194A KR 1019920018178 A KR1019920018178 A KR 1019920018178A KR 920018178 A KR920018178 A KR 920018178A KR 940010194 A KR940010194 A KR 940010194A
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South Korea
Prior art keywords
transition metal
diffusion barrier
wiring layer
semiconductor device
contact hole
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KR1019920018178A
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English (en)
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KR960002061B1 (ko
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박창수
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김광호
삼성전자 주식회사
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Priority to KR1019920018178A priority Critical patent/KR960002061B1/ko
Priority to JP19139693A priority patent/JP3245269B2/ja
Priority to DE4329260A priority patent/DE4329260B9/de
Priority to US08/117,580 priority patent/US5502004A/en
Publication of KR940010194A publication Critical patent/KR940010194A/ko
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Publication of KR960002061B1 publication Critical patent/KR960002061B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

반도체 장치의 배선층 형성방법이 개시되어 있다. 불순물 확산영역이 형성된 반도체 기판상에 절연막을 형성하고, 상기 절연막에 반도체기판의 불순물 확산영역을 노출하는 접촉구를 제공하고, 상기 접촉구의 내면 및 상기 접촉구에 의해 노출된 반도체 기판의 표면상에 확산 방지막을 형성하고, 진공 챔버에서 450℃ 내지 650℃의 온도에서, 일정한 시간동안 상기 확산 방지막을 열처리한다. 접촉 저항값이 확산층의 종류와 무관하게 크게 낮아졌고 균일성도 5%이하로 되어 균일성 개선도 현저하다.

Description

반도체장치의 배선층 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제5도는 본발명의 방법에 의한 반도체장치의 배선층 형성방법의 다른 실시예를 나타내기 위한 도면이다.

Claims (8)

  1. 불순물 확산영역이 형성된 반도체 기판상에 절연막을 형성하고, 상기 절연막에 반도체기판의 불순물 확산영역을 노출하는 접촉구를 제공하고, 상기 접촉구의 내면 및 상기 접촉구에 의해 노출된 반도체 기판의 표면상에확산 방지막을 형성하고, 진공 챔버에서 450℃ 내지 650℃의 온도에서, 일정한 시간동안 상기 확산 방지막을 열처리하는 것을 특징으로 하는 반도체장치의 배선층 형성방법.
  2. 제1항에 있어서, 상기 열처리를 2분 내지 1시간동안 수행함을 특징으로 하는 반도체 장치의 배선층 형성방법.
  3. 제1항에 있어서, 상기 확산방지막은 천이금속, 천이금속합금 및 천이금속화합물로 구성된 군에서 선택된 어느 하나이상으로 이루어짐을 특징으로 하는 반도체장치의 배선층 형성방법.
  4. 제3항에 있어서, 상기 확산방지막은 천이금속으로 구성된 제1확산방지막과 상기 제1확산방지막상에 형성된 천이금속 화합물 또는 천이금속합금으로 구성된 제2확산방지막으로 구성됨을 특징으로 하는 반도체장치의 배선층 형성 방법.
  5. 제3항 또는 제4항에 있어서, 상기 천이금속이 Ti이고 상기 천이금속화합물은 TiN이고, 상기 천이금속합금은 TiW임을 특징으로 하는 반도체장치의 배선층 형성방법.
  6. 제1항에 있어서, 상기 진공 챔버는 4mTorr이하의 불활성 가스분위기에서 유지됨을 특징으로 하는 반도체장치의 배선층 형성방법.
  7. 제6항에 있어서, 상기 불활성가스는 아르곤, 질소 및 헬륨으로 구성된 군에서 선택된 어느 하나의 가스임을 특징으로 하는 반도체장치의 배선층 형성방법.
  8. 제1항에 있어서, 상기 확산방지막을 형성한 후, 대기에 노출지 않고 연속적으로 열처리공정을 수행함을 특징으로 하는 반도체장치의 배선층 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920018178A 1992-10-05 1992-10-05 반도체 장치의 배선층 형성방법 KR960002061B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019920018178A KR960002061B1 (ko) 1992-10-05 1992-10-05 반도체 장치의 배선층 형성방법
JP19139693A JP3245269B2 (ja) 1992-10-05 1993-08-02 半導体装置の製造方法
DE4329260A DE4329260B9 (de) 1992-10-05 1993-08-31 Verfahren zur Herstellung einer Verdrahtung in einem Halbleiterbauelement
US08/117,580 US5502004A (en) 1992-10-05 1993-09-07 Method for manufacturing a semiconductor device with heat treated diffusion layers

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Application Number Priority Date Filing Date Title
KR1019920018178A KR960002061B1 (ko) 1992-10-05 1992-10-05 반도체 장치의 배선층 형성방법

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KR940010194A true KR940010194A (ko) 1994-05-24
KR960002061B1 KR960002061B1 (ko) 1996-02-10

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US (1) US5502004A (ko)
JP (1) JP3245269B2 (ko)
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DE (1) DE4329260B9 (ko)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09116009A (ja) * 1995-10-23 1997-05-02 Sony Corp 接続孔の形成方法
TW319891B (en) * 1996-02-02 1997-11-11 Taiwan Semiconductor Mfg Method for improved aluminium-copper deposition and robust via contact resistance
US5554565A (en) * 1996-02-26 1996-09-10 Taiwan Semiconductor Manufacturing Company Ltd. Modified BP-TEOS tungsten-plug contact process
DE19621855C2 (de) 1996-05-31 2003-03-27 Univ Dresden Tech Verfahren zur Herstellung von Metallisierungen auf Halbleiterkörpern unter Verwendung eines gepulsten Vakuumbogenverdampfers
US6482734B1 (en) 1998-01-20 2002-11-19 Lg Semicon Co., Ltd. Diffusion barrier layer for semiconductor device and fabrication method thereof
US20090026618A1 (en) * 2007-07-25 2009-01-29 Samsung Electronics Co., Ltd. Semiconductor device including interlayer interconnecting structures and methods of forming the same

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61183942A (ja) * 1985-02-08 1986-08-16 Fujitsu Ltd 半導体装置の製造方法
US5010032A (en) * 1985-05-01 1991-04-23 Texas Instruments Incorporated Process for making CMOS device with both P+ and N+ gates including refractory metal silicide and nitride interconnects
US5278099A (en) * 1985-05-13 1994-01-11 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device having wiring electrodes
JPS62109341A (ja) * 1985-11-07 1987-05-20 Mitsubishi Electric Corp 半導体装置の製造方法
JPS6384024A (ja) * 1986-09-26 1988-04-14 Seiko Epson Corp 半導体装置の製造方法
JP2776826B2 (ja) * 1988-04-15 1998-07-16 株式会社日立製作所 半導体装置およびその製造方法
JPH01276743A (ja) * 1988-04-28 1989-11-07 Fujitsu Ltd 半導体装置の製造方法
US4985372A (en) * 1989-02-17 1991-01-15 Tokyo Electron Limited Method of forming conductive layer including removal of native oxide
DD291877A5 (de) * 1990-01-31 1991-07-11 Mikroelektronik "Karl Marx" Erfurt,De Verfahren zum herstellen selbstjustierender silizidkontakte auf halbleiteranordnungen
DE69033234T2 (de) * 1990-02-20 2000-02-03 St Microelectronics Srl Verfahren zur mehrschichtigen Metallisierung der Rückseite einer Halbleiterscheibe
US5094981A (en) * 1990-04-17 1992-03-10 North American Philips Corporation, Signetics Div. Technique for manufacturing interconnections for a semiconductor device by annealing layers of titanium and a barrier material above 550° C.
US5236868A (en) * 1990-04-20 1993-08-17 Applied Materials, Inc. Formation of titanium nitride on semiconductor wafer by reaction of titanium with nitrogen-bearing gas in an integrated processing system
DE4028776C2 (de) * 1990-07-03 1994-03-10 Samsung Electronics Co Ltd Verfahren zur Bildung einer metallischen Verdrahtungsschicht und Füllen einer Kontaktöffnung in einem Halbleiterbauelement
JPH0467622A (ja) * 1990-07-09 1992-03-03 Fujitsu Ltd 半導体装置の製造方法
JPH0677216A (ja) * 1990-09-28 1994-03-18 Applied Materials Inc 蒸着薄膜の障壁特性を高めるプラズマアニーリング法
FR2670605B1 (fr) * 1990-12-13 1993-04-09 France Etat Procede de realisation d'une barriere de diffusion electriquement conductrice a l'interface metal/silicium d'un transistor mos et transistor correspondant.
DE4200809C2 (de) * 1991-03-20 1996-12-12 Samsung Electronics Co Ltd Verfahren zur Bildung einer metallischen Verdrahtungsschicht in einem Halbleiterbauelement
US5270254A (en) * 1991-03-27 1993-12-14 Sgs-Thomson Microelectronics, Inc. Integrated circuit metallization with zero contact enclosure requirements and method of making the same
KR940004256B1 (en) * 1991-04-09 1994-05-19 Samsung Electronics Co Ltd Making method of semiconductor device
US5242860A (en) * 1991-07-24 1993-09-07 Applied Materials, Inc. Method for the formation of tin barrier layer with preferential (111) crystallographic orientation
US5240880A (en) * 1992-05-05 1993-08-31 Zilog, Inc. Ti/TiN/Ti contact metallization

Also Published As

Publication number Publication date
US5502004A (en) 1996-03-26
JP3245269B2 (ja) 2002-01-07
DE4329260A1 (de) 1994-04-07
DE4329260B4 (de) 2007-01-25
KR960002061B1 (ko) 1996-02-10
JPH06196572A (ja) 1994-07-15
DE4329260B9 (de) 2007-05-24

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