KR940003563B1 - 반도체 장치 및 그 제조방법 - Google Patents

반도체 장치 및 그 제조방법 Download PDF

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Publication number
KR940003563B1
KR940003563B1 KR1019900018073A KR900018073A KR940003563B1 KR 940003563 B1 KR940003563 B1 KR 940003563B1 KR 1019900018073 A KR1019900018073 A KR 1019900018073A KR 900018073 A KR900018073 A KR 900018073A KR 940003563 B1 KR940003563 B1 KR 940003563B1
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South Korea
Prior art keywords
ball
electrode pad
semiconductor device
semiconductor element
wire
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KR1019900018073A
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English (en)
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KR910015024A (ko
Inventor
기요아끼 스무라
Original Assignee
미쓰비시 뎅끼 가부시끼가이샤
시기 모리야
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Publication of KR910015024A publication Critical patent/KR910015024A/ko
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Publication of KR940003563B1 publication Critical patent/KR940003563B1/ko

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    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L21/603—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving the application of pressure, e.g. thermo-compression bonding
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Abstract

내용 없음.

Description

반도체 장치 및 그 제조방법
제1도는 본 발명의 한 실시예에 의한 반도체장치를 표시하는 단면도.
제2도는 Cu 볼 형성후의 와이어 본드 공정을 표시하는 구성도.
제3도 및 제5도는 Al 전극패드(pad)에 Cu 볼을 접합한 상태를 표시하는 단면도.
제4도는 Cu 볼의 형성으로부터 Al 전극패드에 Cu 볼이 접속하기까지의 시간과 Cu 볼의 높이와의 관계를 표시하는 선도.
제6도는 본 발명 및 종래의 반도체장치의 고온 유지수명의 시험결과를 표시하는 와이불·풀로트 도면.
제7도는 이 발명 및 종래의 반도체장치의 내습성 시험결과를 표시하는 와이불 풀로트 도면.
제8a도 및 제8b도는 본딩된 초산(礎酸)에 의하여 에칭을 한 후의 Al 전극패드의 각각의 평면도, 측면단면도.
제9도는 다이본딩 후의 반도체소자를 인산용액중에 담근 경우의 유리 코트 크랙을 구조 해석한 평면도.
제10도 및 제11도는 종래의 반도체장치를 표시하는 단면도.
제12a도 및 제12b도는 종래의 반도체장치의 Al 전극패드를 구조 해석한 평면도와 측면단면도.
제13a도 및 제13b도는 종래의 다이본드 후의 반도체장치를 표시하는 각각의 사시도 측면단면도.
제14도는 다이본드 후의 반도체소자를 인산용액중에 담근 경우의 유리 코트 크랙을 구조 해석한 평면도.
* 도면의 주요부분에 대한 부호의 설명
1 : 반도체소자 2,9 : 은도금
3 : 다이스 패드 4 : 에폭시수지
5 : Al 전극패드 6 : 유리코트
7 : 인너리드 8 : Cu 와이어
8a : Cu볼 8b : 오목한 부분
11 : Al 배척부 12 : Al막
13 : SiO2막 14 : 알루미늄 배선
15 : 크랙 16 : Al 매탈라이즈 층
17 : 땜납 18,18a : 케필러리팁
19 : 히트블럭 또한, 각 도면중, 동일부호는 동일 또는 상당부분을 표시한다.
이 발명은 와이어 재료에 동극세선(銅極細線)(Cu 와이어)을 사용하고, 반도체 소자를 다이스 패드에 고정하는 다이본드 재료의 물성을 개선한 반도체 장치와, 동 볼(Cu ball)이 알루미늄(Al) 전극 패드에 접속할 때까지를 소정의 시간에서 행하고 다시금 압축 후의 Cu 볼을 소정의 높이로 하는 반도체 장치의 제조방법에 관한 것이다.
제10도는 종래의 반도체 장치를 표시하는 단면도이며, 도면에 있어서, 반도체 소자(1)는 표면에 은 도금(2)이 된 리드 후레임의 다이스 패드(3) 위에 다이본드 재료인 에폭시수지(4)에 의하여 고정되어 있다. 반도체 소자(1)의 표면에, Al 전극패드(5)가 설치되어 있고, 이 Al 전극패드(5) 이외의 부분은, 뒤의 공정으로 통하여 막아지는 수지로부터의 불순물에 의하여 Al 배선이 부식하는 것을 방지하기 위하여, SiO2인 유리코드(6)로 덮혀 있다.
Al 전극패드(5)와 인너 리드 와이어(7)는 Cu 와이어(8)에 의해 배선(와이어 본드)되어 전기적으로 접속되어 있다. 또한 이 인너 리드(7)의 표면에도 은 도금(9)이 되어 있고, 다이스 패드(3) 및 인너 리드(7)는 똑같이 동 합금 또는 철 니켈 합금을 재료로 하여 제조되어 있다.
제11도는 종래의 다른 반도체 장치를 표시하는 단면도이며, 다이 본드 재료로서 Al-Si(금-실리콘) 땜납(10)을 사용한 이외에는 제10도에 표시한 반도체 장치와 마찬가지이다.
종래의 반도체 장치는 상기한 것과 같이 구성되고, 일반적으로 다이본드 재료의 선택은 다이 본드시의 가열 온도에 의한 반도체 소자의 열화와, 와이어 본드시의 접합 불량의 원인으로 된다는 것을 주로 고려하지 않으면 아니된다.
우선, 다이 본드 재료로서 에폭시 수지(4)를 사용한 경우, 에폭시 수지(4)를 경화하기 위하여 150℃~250℃의 온도를 가하나, 이 온도는 저온이므로 반도체 소자(1)는 거의 열화하지 않는다. 그러나, 와이어 본드시에, 문제가 발생한다.
제12a도 및 제12b도는, 에폭시 수지(4)로 다이본드한 반도체 소자(1)의 Al 전극 패드(5)에 Cu 볼을 본딩한 후, 추산(NHO3)을 사용하여 에칭한 후에 있어서의 Al 전극 패드(5)의 각 평면도 및 측면 단면도이다. 이들의 도면에 의하면, Al 배척이 Al 배척부(11)에서 과도하게 발생되어서, Al 전극 패드(5)의 Al막(12)의 하부층인 SiO2막(13)이 노출되어 버려, 예를들면, 일본국 특개평 1-143332호 공보에 기재되어 있는 것과 같이, 고온보존의 신뢰성이 저하한다.
또, Al 배척의 원인으로 되는 초음파 에너지를 저하시키면 Cu-Al합금층이 충분히 생성되지 않으며, 마찬가지로 고온 보존의 신뢰성이 저하한다. 이 원인은, 와이어 본드 온도가 250℃~300℃, 에폭시수지의 유리전이 온도(glsaa transition temperature)(Tg)가 110℃~150℃ 정도 이므로, 반도체 소자(1)의 고정이 충분치 않은 상태에서, 종래의 Au볼 보다도 가공 경화성이 큰 Cu 볼을 사용함에도 불구하고, 이것을 Au 볼 이상의 진동 에너지를 인가하면서 Al 전극패드(5) 위에서 소성변형시키기 위한 것이라고 추정된다.
다음에, 다이 본드 재료로서 Au-Si 땜납(10)을 사용한 경우, 다이본드 온도는 Au-Si 땜납의 액상성 온도인 (液相線 溫度 ; liquidus temperature)인 370℃ 이상으로 되어, 유리코트(6)에 크랙(Crack)이 발생하고, 반도체 소자(1)가 열화하는 원인으로 된다. 이것을 아래에 설명한다.
제13a도는, 다이 본드 후의 반도체 소자(1) 및 다이스 패드(3)등을 표시하는 사시도이며, 제13b도는 제13a도의 A-A선에 따른 단면도이다. 이 도면들에 있어서, Al 배선(14)은 유리코드(6)로 완전히 덮혀 있다.
와이어 본드 후의 구조 해석에 의하여 Au-Si 땜납(10)으로 다이본드된 것을 80%~90%의 인산(H3PO4)용액 중에 20분간 담그면, 제14도에 표시한 것과 같이 Al 배선(14)이 에칭된 유리 코드(6)에 크랙(15)이 생겨, 수지로 봉하여 막은 후의 내습성을 열화시키게 되는 것을 알게 된다
이 크랙(15)의 발생 원인은, 유리 코드(6) 및 반도체 소자(1)의 열 팽창 계수의 차(유리 코드 SiO2: 0.65×10-6/℃, 반도체 소자의 Si : 3.5×10-6/℃)에 의하여, Al 배선(14)위의 유리 코드(6) 부분에 응력이 집중하여, 크랙(15)에 이르는 것이라고 추정된다. 또한 다이 본드재로서 Au-Si 땜납(10)을 사용하는 이유는, Cu 와이어와 Al 전극의 상호 확산을 촉진하도록, 와이어 본드 온도를 Au 와이어를 사용한 경우 이상으로 상승시키기 위한 것이다.
상술한 것과 같은 반도체 장치에서, 다이본드재로 에폭시 수지를 사용한 경우에는, 와이어 본드 가열 온도가 에폭시 수지의 유리전이 온도이상이기 때문에 반도체 소자의 고정이 충분하지 않은 상태에서, Au 볼 보다도 가공 경화성이 큰 Cu 볼에 Al 볼 이상의 초음파 진동 에너지를 인가하면서 Al 전극 패드 위에서 소성변형시키기 위하여, Al 전극패드의 Al을 배척하고, 하부 SiO2막을 노출시키므로, 반도체 장치의 고온보존 수명을 저하시키는 것이 된다.
또, 와이어 본드의 가열온도를 Au 와이어를 사용한 경우보다 높게 설정하는 목적으로 Au-Si 땜납을 사용한 경우, 다이본드시의 가열 온도에서 반도체 소자의 유리 코트에 크랙이 발생하여, 내습성 수명을 저하시키고, 더우기 좋은 장점이 없어지고마는 문제점이 있었다.
이 발명은, 이러한 문제점을 해결하기 위하여 이루어진 것이며, 반도체 소자 다이스 패드 위에 단단히 고정할 수 있음과 아울러 유리 코트 크랙이 발생하지 않는 온도에서 다이본딩할 수 있는 다이본드 재료를 사용하여 Cu 와이어를 본딩한 반도체 장치를 얻는 것을 목적으로 한다.
다시금, Cu 와이어 선단부를 용융하여 형성되는 Cu 볼이, 온도를 유지하는 것에 의하여 표면 산화막의 성장이나 Cu 볼의 경도가 높게 되는 것을 억제하고, 압착시에 인가되는 초음파 진동에 의하여 Cu와 Al의 원자를 효율좋게 진동시켜서, Al 배척이 이르지 않은 반도체 장치의 제조방법을 얻는 것을 목적으로 한다.
이 발명에 관한 반도체 장치는, 유리 코트와 Al 전극 패드와의 열팽창 차(差)에 의한 크랙을 발생시키지 않는 액상선 온도를 가지는 땜납에 의하여, 반도체소자를 다이스 패드위에 고착한 것이다.
또 이 발명의 별도의 발명에 관한 반도체 장치의 제조 방법은, 동 와이어의 선단부를 용융하여 형성된 동볼을, 150ms(미리초)이내의 시간으로 반도체 소자위의 Al 전극 패드까지 강하, 접촉하여 소성변형을 개시하고 동 볼의 높이가 25㎛이하로 되도록 동 볼을 상기 Al 전극 패드에 눌러 접촉하는 것이다.
이 발명에 있어서는, 유리 코트에 크랙을 발생시키지 않고, 다이스 패드의 온 도금과 반도체 소자의 이면에 형성된 Au 메탈라이즈층에 의하여, 반도체 소자 전체를 단단하게 다이스 패드 위에 고정시킬 수가 있다.
또한 이 발명의 별도의 발명에 있어서는, Cu 볼의 성형으로부터 Au 전극 패드에 접촉할 때까지의 시간과, 압축시의 Cu 볼의 높이를 소정의 값으로 하는 것에 의하여, Cu 볼의 가공 경화성을 저하시켜 Cu 볼을 Al 전극 패드에 접합할 때에 Al이 배척되는 것을 방지한다.
[실시예]
이 발명의 종래기술과 크게 다른점은, 우선 첫째, 종래기술에서는 와이어재가 Au로부터 Cu로 변화된 것에 의하여 극복하여야 할 점을 명확하게 분석하지 않았으므로, 제품의 신뢰성을 높이거나, 양산가능한 제조기술로 확립되어 있지 않았다는 것이다.
이것에 대하여 이 발명에서는 Au 볼 이상으로 가공 경도성이 큰 Cu 볼의 소성변형을 개선하는 것을 우선적으로 고려하여, 초음파 진동을 확실하게 Cu 볼과 Al 전극 패드에 작용시키기 위하여, 땜납게의 다이본드 재료를 선택하였다. 둘째는, 반도체 소자의 가열 온도가 유리 코트 크랙을 발생시키지 않게 할 필요성으로부터, 종래 실적이 있는 Pb-5% Sn 땜납 등 액상선 온도가 370℃이하의 것을 선택하였다.
최후로, Cu 볼의 소성변형성을 나쁘게 하는 Cu 볼 표면의 산화막의 성장을 막고, Cu 볼 자체가 유지하는 열을 활용하기 위하여는, Cu 볼의 형성부터 Al 전극 패드에 접촉할 때까지의 시간을 150ms 이하로 하여, 초음파 에너지를 효율좋게 작용시키기 위하여, Cu 볼의 압착높이를 가능한한 작게, 즉 25㎛ 이하로 하는 것이다.
이하, 도면에 의거하여, 본 발명은 다시금 상세하게 설명한다.
제1도는 이 발명의 한 실시예를 표시하는 단면도이며, (1)~(3), (5)~(9)는 상술한 종래의 반도체 장치에 있어서의 것과 동일하다.
반도체 소자(1)의 이면에는 Au 메탈라이즈층(16)으로서 예를들면 Ti-Ni-Au가 시행되어 있고, 이 메탈리이즈층(16)과 다이스 패드(3) 위의 은 도금(2)과의 사이에는 땜납(17)로서 예를들면 Pb-5% Sn 땜납을 개재시키는 것에 의하여, 반도체 소자(1)를 다이스 패드(3) 위에 고정하고 있다.
제2도는 Cu 볼 형성 후의 와이어볼드 공정을 표시하는 구성도이며, Cu 볼(8a)을 Al 전극 패드(5)위에 눌러 접속하는 캐필러리 팁(capillary tip)(18)이, 반도체소자(1))의 윗쪽에 배치되어 있다.
또, 다이스 패드(3)의 아래에는, 다이스 패드(3)를 가열하기 위한 히트블럭(heat block)(19)이 설치되어 있다.
상술한 것과 같이 구성된 반도체 장치에 있어서 Cu 볼(8a)은, 제3도에 표시한 것과 같이, 캐필러리 팁(18)과 아울러 Al 전극 패드(5)위에 강하하고, 캐필러리 팁(18)으로부터의 하중(약 150g)과 초음파 진동 에너지 및 히트블럭(19)으로부터의 열 에너지(약 280℃)에 의하여 Al 전극 패드(5)와 접합한다.
여기서, Cu 볼(8a)의 소성변형을 정량적으로 파악하기 위해서는, 일정한 초음파 진동 에너지를 캐필러리 팁(18)에 가하여 Cu 볼(8a)를 Al 전극 패드(5)에 접한 후, 이 Cu 볼(8a)의 높이(h)를, Cu볼(8a)의 형성으로부터 Al 전극 패드(5)에 접촉할 때까지의 시간(t)을 변화시켜서 측정하였다. 그 결과를 제4도에 표시한다.
이 도면에서, 상기 시간(t)가 15ms 이내에서는 Cu볼(8a)의 불균형이 적으며 양호하거나, 150ms를 넘으면 Cu 볼(8a)의 높이가 일정하게 되지않고 불균형이 크게 되므로 바람직하지 않다. 따라서, 시간(t)가 짧을 수록 Cu 볼(8a)의 소성변형이 양호하여, 제조장치의 기계적인 제약으로부터 판단하여도, 150ms이내가 가장 좋은 조건이라는 것을 알게 된다.
다시금, 가장 적당한 것은 120ms 이하이며, 150ms~100ms에 있어서 우수한 결과를 얻을 수가 있다. 또, 눌러접속한 후의 Cu 볼(8a)의 높이가 25㎛ 이하에서는 반도체 소자(1)로의 손상은 없고, Cu-Al 합금도 양호하게 생성하지만, Cu 볼(8a)의 높이가 25㎛을 초과하면, 반도체 소자(1)로의 손상이 생겨, 동시에 합금의 생성이 불충분하게 되면, 신뢰성을 저하시키는 원인으로 된다.
또한, Cu 볼(8a)의 높이(h)는 제5도에 표시하는 캐필러리 팁(18a)의 경우에는 Cu 볼(8a)의 오목한 부분(8b)과 Al 전극 패드(5)의 최단거리를 표시하는 것으로 한다.
또, 제4도에 있어서, A는 생성한 Cu 볼(8a)의 지름이 작을 경우, B는 생성된 Cu 볼(8a)의 지름이 큰 경우이다. 통상, Cu 와이어(8)의 외경은 25㎛정도, 눌러 접속된 Cu 볼(8a)의 외경은 100㎛ 이하이다.
다음에 수지로 봉하여 막은 후의 반도체 장치의 200℃에 있어서의 고온보존수명을 평가하는 시험을 행한바, 제6도에 표시하는 결과를 얻었다.
이 도면에서 명백한 바와같이, 본 발명에 의한 반도체장치의 고온보존수명(도면에 C로 표시함)은, 종래의 반도체 장치의 고온 보존 수명(도면에 D로 표시함)에 비교 하여 개선효과가 보여졌다.
마찬가지로 121℃, 100%RH이 있어서의 내습성이 시험을 행하여, 이것을 평가하면, 제7도의 와이불 풀로트(Weibull Plot)도에 표시한 것과 같이 이 발명에 의한 반도체 장치의 특성(도면에서 F로 표시함)은 종래의 반도체 장치(도면에서 F로 표시함)에 비교하여 개선효과가 보였다. 이것들은 반도체 소자의 구조해석에 의해서도 뒷받침되었다. 즉, 본딩된 Cu 볼(8a)을 초산(HNO3)을 사용하여 에칭한후의 Al 전극 패드(5)의 평면도 및 측면 단면도를 각각 제8a도 및 제8b도에 표시한다.
이들의 도면에서 명백한 바와같이, 소량의 Al 배척이 일어나 Al 배척부(11)가 생길 뿐, 하부의 SiO2막(13)은 노출되고 있지 않다.
또, 제9도에 표시한 것과 같이 다이본드 후의 반도체 소자(1)를 80℃~90℃의 인산(H3PO4)용액 속에 20분간 담궈도 Al 배선(14)이 부식되지 않고, 유리코트 크랙도 발생하지 않는다.
또한, 상술한 실시예에서는 땜납 재로서 Pb-5%Sn땜납을 사용하였으나, 액상선 온도가 370℃이하인 것이라면, 다른 어떠한 땜납일 지라도, 마찬가지로 사용할 수가 있다. 예를들면 Pb-Sn(5%이상 Sn) Pb-Ag, Pb-In, Sn-Ag, Pb-Ag-Sn, Pb-Ag-In 등의 땜납을 사용할 수 있다.
다시금, 금 메탈라이즈층(16)으로서, Ti-Ni-Au를 사용하였으나, 표면이 Au 또는 Ag로 메탈라이즈되어 있어도 좋고, 메탈라이즈층으로서는 Ag 메탈라이즈층이라도 좋으며, 예를들면 CR-Ag 등이 사용될 수 있다.
또, 반도체 소자(1)는 플레이너형의 IC가 아닌 유리 코트가 없는 것, 또는 SiO2막 등의 절연막이 없는 트랜지스터라도 좋고, 기판 자체 Si이외의 GaAs등의 화합물 반도체라도 좋다. 다시금 Al 전극 패드(5)의 Al 합금의 하부구조는 SiO2막에 한정하는 것은 아니면, 다른 재료에 의한 부재라도 좋다.
이 발명은 이상에서 설명한 것과 같이, 리드 후레임의 다이스 패드와, 이 다이스 패드 위에 설치되고 Al 전극 패드 및 유리 코트를 가지는 반도체 소자와, 이 반도체 소자의 상기 다이스 패드를 고착하고 상기 유리 코트의 상기 Al 전극 패드와의 열팽창 차에 의한 크랙을 발생시키지 않는 액상선 온도를 가지는 땜납과, 상기 Al 전극 패드에 와이어 본딩된 동 와이어를 구비한 것으로서, 다이스 패드 위에 반도체 소자를 단단하게 고정함과 아울러, 유리 코트 크랙의 발생을 억제할 수 있다는 효과를 이룬다. 또, 동 와이어 선단부를 용융하여 동 볼을 형성하고, 이 동볼의 형성으로부터 150ms 이내의 시간내에서 상기 동볼을 반도체소자 위의 Al 전극 패드까지 강하, 접속시켜, 계속하여 이어서 상기 동볼의 높이가 25㎛ 이하로 되도록 동볼을 상기 Al 전극 패드에 눌러 접속하므로, 소성변형성이 양호한 상태로 Al 전극 패드와 Cu 볼을 접합시킬 수가 있다.
다시금, 초음파 진동을 확실하게 Cu 볼과 Al 전극 패드에 작용시켜서, Al 배척의 발생을 억제할 수가 있다.
또, 최대의 장점은, Au 와이어의 본딩 프로세스를 거의 변화없이 Cu 와이어의 본딩을 행할 수가 있으므로 제품으로서의 실용가능한 신뢰성을 확보할 수가 있다는데 있다.

Claims (2)

  1. 리드 프레임의 다이스 패드(3) 위에 Cu 볼(8a)과 캐필러리 팁(18)을 설치하고 알루미늄전극패드(5) 및 유리 코트를 가지는 반도체 소자(1)에 상기 다이스패드를 땜납으로 고착하는 것에 있어서, 상기 유리 코트와 상기 알루미늄 전극 패드와의 열팽창차에 의한 크랙을 발생시키지 않는 액상선 온도를 가지는 땜납(17)과, 상기 알루미늄 전극 패드에 와이어 본딩된 동극세선을 구비한 것을 특징으로 하는 반도체 장치.
  2. 동극세선의 선단부를 용융하여 동 볼을 형성하고, 이 동 볼의 형성으로부터 150ms 이내의 시간으로 상기 동 볼을 반도체소자 위의 Al 전극 패드까지 강하, 접속시켜, 계속하여, 상기 동 볼의 높이가 25㎛이하로 되도록 동 볼을 상기 알루미늄 전극 패드에 눌러 접속하는 것을 특징으로 하는 반도체 장치의 제조방법.
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GB1457806A (en) * 1974-03-04 1976-12-08 Mullard Ltd Semiconductor device manufacture
DE2428373C2 (de) * 1974-06-12 1982-05-27 Siemens AG, 1000 Berlin und 8000 München Verfahren zum Herstellen von weichlötbaren Anschlußkontakten auf einer Halbleiteranordnung
DE2628433B2 (de) * 1976-06-24 1978-09-07 Focke & Pfuhl, 3090 Verden Packung mit Schieber und Hülse
JPS5321771A (en) * 1976-08-11 1978-02-28 Sharp Kk Electronic parts mounting structure
JPS586143A (ja) * 1981-07-02 1983-01-13 Matsushita Electronics Corp 半導体装置
JPS5873127A (ja) * 1981-10-28 1983-05-02 Hitachi Ltd Ｉｃチツプのはんだ溶融接続方法
CH662007A5 (en) * 1983-12-21 1987-08-31 Bbc Brown Boveri & Cie Method of soldering semiconductor components
DE3523808C3 (de) * 1984-07-03 1995-05-04 Hitachi Ltd Verfahren zum Löten von Teilen einer elektronischen Anordnung aus unterschiedlichen Werkstoffen und dessen Verwendung
DE3446780A1 (de) * 1984-12-21 1986-07-03 Brown, Boveri & Cie Ag, 6800 Mannheim Verfahren und verbindungswerkstoff zum metallischen verbinden von bauteilen
GB2178683A (en) * 1985-07-11 1987-02-18 Nat Semiconductor Corp Improved semiconductor die-attach method and product
DE3641524A1 (de) * 1985-12-10 1987-06-11 Mitsubishi Electric Corp Verfahren zur herstellung eines halbleiterbauelements
DE3641689A1 (de) * 1985-12-24 1987-06-25 Mitsubishi Electric Corp Verfahren zur herstellung eines halbleiterbauelements und eines darin verwendeten halbleiterchips
JPS63148646A (ja) * 1986-12-12 1988-06-21 Toshiba Corp 半導体装置
JPH0748507B2 (ja) * 1987-08-18 1995-05-24 三菱電機株式会社 ワイヤボンデイング方法
JPH01201934A (ja) * 1988-02-08 1989-08-14 Mitsubishi Electric Corp ワイヤボンディング方法及びキャピラリチップ
JPH0817189B2 (ja) * 1989-01-13 1996-02-21 三菱電機株式会社 半導体装置の製造方法

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DE4021031A1 (de) 1991-07-11
DE4021031C2 (de) 1995-04-20
KR910015024A (ko) 1991-08-31
JPH03208355A (ja) 1991-09-11
GB2239829B (en) 1994-07-06
GB2239829A (en) 1991-07-17
SG155894G (en) 1995-03-17
GB9010385D0 (en) 1990-06-27

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