KR930018692A - 반도체장치의 제조방법 - Google Patents

반도체장치의 제조방법 Download PDF

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Publication number
KR930018692A
KR930018692A KR1019920002927A KR920002927A KR930018692A KR 930018692 A KR930018692 A KR 930018692A KR 1019920002927 A KR1019920002927 A KR 1019920002927A KR 920002927 A KR920002927 A KR 920002927A KR 930018692 A KR930018692 A KR 930018692A
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well
region
manufacturing
forming
memory cell
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KR1019920002927A
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KR950005464B1 (ko
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김영필
정태영
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김광호
삼성전자 주식회사
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Priority to KR1019920002927A priority Critical patent/KR950005464B1/ko
Priority to JP5036338A priority patent/JP2531481B2/ja
Priority to US08/022,637 priority patent/US5766970A/en
Publication of KR930018692A publication Critical patent/KR930018692A/ko
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Publication of KR950005464B1 publication Critical patent/KR950005464B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/96—Porous semiconductor

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 이중웰 이상의 CMOS 구조로 된 고집적 반도체 메모리장치에 있어서 메모리셀 영역과 주변부간의 단차를 줄일수 있는 반도체장치의 제조방법에 관한 것으로, 본 발명은 웰 형정시 통상의 방법과 반대로 P웰을 먼저 형성한 후에 N웰을 형성하는 방법, 각가의 웰 형성시 포토리소그래피공정을 통한 포토레지스트를 이온주입마스크로 사용하는 방법, 메모리셀 영역이 될 부분을 산화시킨후 형성된 산화막을 제거하여 메모리셀 영역의 단차를 낮추는 방법 및 메모리셀 영역의 될 부분에 다공성 실리콘을 형성하고 산화시킨후 산화막을 제거하여 메모리셀 영역의 단차를 낮추는 방법을 제공한다. 따라서 본 발명에 의하면 초고집적 반도체 메모리장치에 있어서의 메모리셀 영역과 주변부와의 단차를 줄일 수 있음에 따라 후속공정의 사진식각공정을 용이하게 행할 수 있고 금속 배선형성시 배선의 단락형성을 방지할 수 있게 되어 디바이스의 신뢰성 향상을 도모할 수 있다.

Description

반도체장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3a도 내지 제3c도는 본 발명의 제1실시예를 나타낸 도면.
제4a도 내지 제4c도는 본 발명의 제2실시예를 나타낸 도면.
제5a도 내지 제5c도는 본 발명의 제3실시예를 나타낸 도면.

Claims (10)

  1. 메모리셀 영역이 P웰 영역상에 형성되는 이중웰 구조를 가진 반도체메모리장치의 제조방법에 있어서, N웰 형성공정전에 P웰형성공정을 먼저 행하는 것을 특징으로 하는 반도체장치의 제조방법.
  2. 제1항에 있어서, 상기 P웰 형성공정은 반도체기판상에 산화막과 질화막을 순차 적층하고 포토레지스트를 도포한 뒤에 포토리소그래피 공정을 통하여 P웰이 형성될 영역 이외의 영역에만 상기 포토레지스트를 남긴 다음 P형 불순물을 이온주입하고 후공정인 드라이브인 공정을 실시하는 것임을 특징으로 하는 반도체장치의 제조방법.
  3. 제2항에 있어서, 상기 이온주입되는 P형 불순물의 농도가 1012~1013 cm -2이상인 것을 특징으로 하는 반도체장치의 제조방법.
  4. 제1항에 있어서, 상기 N웰 형성공정은 상기 P월 형성을 위한 불순물을 이온주입한후, 산화공정을 실시하여 P웰 영역상에 두꺼운 산화막을 형성한 다음 N형 불순물을 주입하고 드라이브인 공정을 실시하는 것임을 특징으로 하는 반도체장치의 제조방법.
  5. 제4항에 있어서, 상기 두꺼운 산화막의 두께는 3000Å~6000Å임을 특징으로 하는 반도체장치의 제조방법.
  6. 메모리셀영역이 P웰영역상에 형성되는 이중웰 구조를 가진 반도체메모리장치의 제조방법에 있어서, N웰 형성을 우 한 이온주입공정 후 400Å~600Å두께의 산화막을 N웰 영역상에 형성하고 포토리소그래피공정을 통해 P웰영역 이외의 영역에만 포토레지스트를 남겨 이 포토레지스트를 마스크로하여 P형 불순물을 이온주입하여 P웰을 형성하는 것을 특징으로 하는 반도체장치의 제조방법.
  7. 이중웰 구조를 가진 반도체 메모리장치의 제조방법에 있어서, 반도체기판에 산화막과 질화막을 순차 적층한 후 포토리소그래피공정을 통하여 메모리셀 영역이 될 부분의 포토레지스트와 상기 질화막을 제거한 다음 산화공정을 실시하여 상기 메모셀 영역상에 두꺼운 산화막을 형성한후, 상기 남아 있는 질화막, 산화막 및 두꺼운 산화막을 제거하는 것을 특징으로 하는 반도체장치의 제조방법.
  8. 제7항에 있어서, 상기 메모리셀 영역이 메모리셀 영역이외의 부분보다 상기 두꺼운 산화막 두께의 약1/2에 해당하는 만큼 낮게 되는 것을 특징으로 하는 반도체장치의 제조방법.
  9. 메모리셀 영역이 P웰 영역상에 형성되는 이중웰구조를 가진 반도체 메모리장치의 제조방법에 있어서, N웰과 P웰을 형성한 다음 단차가 낮은쪽의 웰 영역을 포토레지스트로 마스킹하고 단차가 높은 쪽의 웰영역내에 다공성 실리콘층을 형성한 후 산화시키고 난 다음 형성된 산화막을 모두 제거하는 것을 특징으로 하는 반도체장치의 제조방법.
  10. 제9항에 있어서, 상기 웰 영역내에 다공성 실리콘을 형성하는 공정은 50%HF용액내에서의 양극산화에 의해 행함을 특징으로 하는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920002927A 1992-02-25 1992-02-25 반도체장치의 제조방법 KR950005464B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019920002927A KR950005464B1 (ko) 1992-02-25 1992-02-25 반도체장치의 제조방법
JP5036338A JP2531481B2 (ja) 1992-02-25 1993-02-25 半導体装置の製造方法
US08/022,637 US5766970A (en) 1992-02-25 1993-02-25 Method of manufacturing a twin well semiconductor device with improved planarity

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Application Number Priority Date Filing Date Title
KR1019920002927A KR950005464B1 (ko) 1992-02-25 1992-02-25 반도체장치의 제조방법

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KR930018692A true KR930018692A (ko) 1993-09-22
KR950005464B1 KR950005464B1 (ko) 1995-05-24

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US (1) US5766970A (ko)
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Cited By (1)

* Cited by examiner, † Cited by third party
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Publication number Publication date
JP2531481B2 (ja) 1996-09-04
KR950005464B1 (ko) 1995-05-24
JPH0685201A (ja) 1994-03-25
US5766970A (en) 1998-06-16

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