KR930018654A - 반도체 소자의 콘택홀 형성방법 - Google Patents

반도체 소자의 콘택홀 형성방법 Download PDF

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Publication number
KR930018654A
KR930018654A KR1019920002005A KR920002005A KR930018654A KR 930018654 A KR930018654 A KR 930018654A KR 1019920002005 A KR1019920002005 A KR 1019920002005A KR 920002005 A KR920002005 A KR 920002005A KR 930018654 A KR930018654 A KR 930018654A
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KR
South Korea
Prior art keywords
hard mask
forming
layer
etching process
pattern
Prior art date
Application number
KR1019920002005A
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English (en)
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KR950000658B1 (en
Inventor
윤수식
김진웅
오진성
김일욱
박희국
Original Assignee
김주용
현대전자산업주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김주용, 현대전자산업주식회사 filed Critical 김주용
Priority to KR92002005A priority Critical patent/KR950000658B1/ko
Priority to US08/016,597 priority patent/US5294296A/en
Priority to JP5024290A priority patent/JP2505359B2/ja
Publication of KR930018654A publication Critical patent/KR930018654A/ko
Application granted granted Critical
Publication of KR950000658B1 publication Critical patent/KR950000658B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Abstract

본 발명은 반도체 소자의 콘택홀 형성방법에 관한 것으로, 특히 스페이서(spacer)구조의 하드마스크(Hard Mask)를 식각베리어(Barrier)층으로 사용하여 마스크층의 마모(Erosion)에 따른 콘택홀 크기의 변화와 감광막 패턴으로 형성 불가능한 미세 크기의 콘택홀을 재현성 있게 형성할 수 있는 반도체 소자의 콘택홀 형성방법에 관한 기술이다.

Description

반도체 소자의 콘택홀 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3a 내지 3e도는 본 발명에 이한 반도체 소자의 콘택홀 형성단계를 나타낸 단면도.

Claims (2)

  1. 실리콘 기판상에 절연막층 및 제2하드마스크층을 적층한 후, 설계된 콘택홀의 크기보다 큰 위도우를 갖는 감광막 패턴을 상기 제1하드마스크층상에 형성하는 단계와, 상기 감광막 패턴을 이용하여 비등방성 식각공정으로 제1하드마스크 패턴을 형성한후, 비등방성 식각공정으로 절연막층의 예정깊이까지 식각하여 홈부를 형성한 다음, 감광막 패턴을 제거하는 단계와, 상기 홈부를 포함한 제1하드마스크 패턴상부 전반에 걸쳐 제2하드마스크층을 예정된 두께로 적층한후, 마스크없이 블랭킷 건식식각공정으로 홈부를 내측벽에 제2하드마스크 스페이서를 형성하는 단계와, 상기 제1하드마스크 패턴과 제2하드마스크 스페이서를 식각베리어층으로 하여 비등방성 식각공정으로 실리콘 기판이 노출될때까지 절연막층을 식각하여 콘택홀을 형성하는 단계로 이루어지는 반도체 소자의 콘택홀 형성방법에 있어서, 상기 제1하드마스크 패턴과 제2하드마스크 스페이서를 식각베리어층으로 하여 하부의 절연막층을 식각할때 제2하드마스크 스페이서 상부가 취약하여 모서리부의 절연막층이 식각되는 것을 방지하기 위하여, 상기 감광막 패턴을 이용하여 비등방성 식각공정으로 제1하드마스크 패턴을 형성한후, 등방성 식각공정으로 절연막층의 예정깊이까지 식각하여 홈부를 형성하여서 후공정에서 홈부내측벽까지 제2하드마스크 스페이서가 형성되도록 하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.
  2. 제1항에 있어서, 비등방성 식각공정으로 제1하드마스크 패턴을 형성한후 등방성 식가공정을 실시하지 않고, 제1하드마스크 패턴 공정에서 발생하는 폴리머를 제거하기 위해 실시하는 절연막층 식각용액을 사용하는 후처리 공정에서 절연막층의 예정깊이를 식각하여 홈부를 형성하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR92002005A 1992-02-12 1992-02-12 Forming method of contact hole in semiconductor devices KR950000658B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR92002005A KR950000658B1 (en) 1992-02-12 1992-02-12 Forming method of contact hole in semiconductor devices
US08/016,597 US5294296A (en) 1992-02-12 1993-02-11 Method for manufacturing a contact hole of a semiconductor device
JP5024290A JP2505359B2 (ja) 1992-02-12 1993-02-12 半導体装置のコンタクトホ―ル形成方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR92002005A KR950000658B1 (en) 1992-02-12 1992-02-12 Forming method of contact hole in semiconductor devices

Publications (2)

Publication Number Publication Date
KR930018654A true KR930018654A (ko) 1993-09-22
KR950000658B1 KR950000658B1 (en) 1995-01-27

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR92002005A KR950000658B1 (en) 1992-02-12 1992-02-12 Forming method of contact hole in semiconductor devices

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US (1) US5294296A (ko)
JP (1) JP2505359B2 (ko)
KR (1) KR950000658B1 (ko)

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KR100733211B1 (ko) * 2006-01-23 2007-06-27 주식회사 하이닉스반도체 반도체 소자의 제조 방법

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KR0146246B1 (ko) * 1994-09-26 1998-11-02 김주용 반도체 소자 콘택 제조방법
US5453403A (en) * 1994-10-24 1995-09-26 Chartered Semiconductor Manufacturing Pte, Ltd. Method of beveled contact opening formation
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US5843625A (en) * 1996-07-23 1998-12-01 Advanced Micro Devices, Inc. Method of reducing via and contact dimensions beyond photolithography equipment limits
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US6214727B1 (en) * 1997-02-11 2001-04-10 Micron Technology, Inc. Conductive electrical contacts, capacitors, DRAMs, and integrated circuitry, and methods of forming conductive electrical contacts, capacitors, DRAMs, and integrated circuitry
JP3059159B1 (ja) * 1998-10-19 2000-07-04 沖電気工業株式会社 コンタクトホ―ルの形成方法
US6699792B1 (en) * 2001-07-17 2004-03-02 Advanced Micro Devices, Inc. Polymer spacers for creating small geometry space and method of manufacture thereof
CN115274411B (zh) * 2022-09-27 2023-07-18 粤芯半导体技术股份有限公司 掩膜结构的制备方法、掩膜结构、半导体结构的制备方法

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JP2505359B2 (ja) 1996-06-05
US5294296A (en) 1994-03-15
JPH06216085A (ja) 1994-08-05
KR950000658B1 (en) 1995-01-27

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