KR100425935B1 - 반도체 소자의 콘택홀 형성 방법 - Google Patents
반도체 소자의 콘택홀 형성 방법 Download PDFInfo
- Publication number
- KR100425935B1 KR100425935B1 KR10-2001-0038414A KR20010038414A KR100425935B1 KR 100425935 B1 KR100425935 B1 KR 100425935B1 KR 20010038414 A KR20010038414 A KR 20010038414A KR 100425935 B1 KR100425935 B1 KR 100425935B1
- Authority
- KR
- South Korea
- Prior art keywords
- contact hole
- hard mask
- region
- forming
- mask layer
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 14
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000010410 layer Substances 0.000 claims abstract description 38
- 238000005530 etching Methods 0.000 claims abstract description 16
- 239000011229 interlayer Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000000059 patterning Methods 0.000 claims abstract description 6
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 15
- 238000000151 deposition Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
Claims (2)
- 단차를 가진 하부 구조가 형성되어 있는 반도체 기판의 층간 절연막 상에 하드 마스크층을 형성하는 단계;딥 콘택홀이 형성될 영역을 노출시키도록 상기 하드 마스크층을 제 1 패터닝하는 단계;상기 패터닝된 하드 마스크층을 식각 마스크로 이용하여 상기 딥 콘택홀이 형성될 영역의 상기 층간 절연막을 소정 깊이만큼 1차 식각하는 단계;쉘로우 콘택홀이 형성될 영역을 노출시키도록 상기 하드 마스크층을 제 2 패터닝하여, 상기 딥 콘택홀과 상기 쉘로우 콘택홀을 동시에 식각할 수 있는 하드 마스크 패턴을 형성하는 단계; 및상기 하드 마스크 패턴을 식각 마스크로 이용하여 반도체 기판 및 하부 구조까지 상기 층간 절연막을 2차 식각하여 상기 딥 콘택홀 및 상기 쉘로우 콘택홀을 동시에 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 콘택홀 형성 방법
- 제1항에 있어서, 상기 딥 콘택홀이 형성될 영역을 1차 식각하는 깊이는 상기 딥 콘택홀의 깊이에서 상기 쉘로우 콘택홀의 깊이 만큼을 뺀 깊이인 것을 특징으로 하는 반도체 소자의 콘택홀 형성 방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2001-0038414A KR100425935B1 (ko) | 2001-06-29 | 2001-06-29 | 반도체 소자의 콘택홀 형성 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2001-0038414A KR100425935B1 (ko) | 2001-06-29 | 2001-06-29 | 반도체 소자의 콘택홀 형성 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20030002714A KR20030002714A (ko) | 2003-01-09 |
KR100425935B1 true KR100425935B1 (ko) | 2004-04-03 |
Family
ID=27712413
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR10-2001-0038414A KR100425935B1 (ko) | 2001-06-29 | 2001-06-29 | 반도체 소자의 콘택홀 형성 방법 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100425935B1 (ko) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101132730B1 (ko) * | 2006-12-14 | 2012-04-06 | 에스케이케미칼주식회사 | 위염 또는 위궤양 예방 및 치료에 유용한 모모르디카사포닌i |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0415938A (ja) * | 1990-05-09 | 1992-01-21 | Toshiba Corp | コンタクトホールの形成方法 |
JPH0483336A (ja) * | 1990-07-25 | 1992-03-17 | Fujitsu Ltd | 半導体装置の製造方法 |
US5444020A (en) * | 1992-10-13 | 1995-08-22 | Samsung Electronics Co., Ltd. | Method for forming contact holes having different depths |
KR970013032A (ko) * | 1995-08-21 | 1997-03-29 | 김광호 | 고집적 반도체장치의 콘택트 형성방법 |
-
2001
- 2001-06-29 KR KR10-2001-0038414A patent/KR100425935B1/ko active IP Right Grant
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0415938A (ja) * | 1990-05-09 | 1992-01-21 | Toshiba Corp | コンタクトホールの形成方法 |
JPH0483336A (ja) * | 1990-07-25 | 1992-03-17 | Fujitsu Ltd | 半導体装置の製造方法 |
US5444020A (en) * | 1992-10-13 | 1995-08-22 | Samsung Electronics Co., Ltd. | Method for forming contact holes having different depths |
KR970013032A (ko) * | 1995-08-21 | 1997-03-29 | 김광호 | 고집적 반도체장치의 콘택트 형성방법 |
Also Published As
Publication number | Publication date |
---|---|
KR20030002714A (ko) | 2003-01-09 |
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