KR930015098A - 반도체 메모리장치의 박막트랜지스터 및 그 제조방법 - Google Patents

반도체 메모리장치의 박막트랜지스터 및 그 제조방법 Download PDF

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KR930015098A
KR930015098A KR1019920006678A KR920006678A KR930015098A KR 930015098 A KR930015098 A KR 930015098A KR 1019920006678 A KR1019920006678 A KR 1019920006678A KR 920006678 A KR920006678 A KR 920006678A KR 930015098 A KR930015098 A KR 930015098A
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conductive layer
contact hole
layer
thin film
film transistor
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KR1019920006678A
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KR950001159B1 (ko
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김장래
김한수
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김광호
삼성전자 주식회사
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Priority to KR1019920006678A priority Critical patent/KR950001159B1/ko
Priority to FR9207651A priority patent/FR2685818B1/fr
Priority to GB9213809A priority patent/GB2262838B/en
Priority to US07/906,369 priority patent/US5270968A/en
Priority to ITMI921603A priority patent/IT1255398B/it
Priority to DE4221420A priority patent/DE4221420A1/de
Priority to TW081105179A priority patent/TW212851B/zh
Priority to CN92105269A priority patent/CN1032286C/zh
Priority to JP4187031A priority patent/JPH0773114B2/ja
Publication of KR930015098A publication Critical patent/KR930015098A/ko
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Abstract

내용 없음

Description

반도체 메모리장치의 박막트랜지스터 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1a도는 종래의 반도체 메모리장치의 박막트랜지스터의 평면 레이아웃도.
제1b도는 제1a도의 a-a 선에 따른 박막트랜지스터의 단면도.
제2a도는 본 발명에 의한 반도체 메모리장치의 박막트랜지스터의 평면 레이아웃도.
제2b도는 제2a도의 a-a선에 따른 박막트랜지스터의 단면도.
제3a도~제3e도는 본 발명에 의한 반도체 메모리장치의 박막트랜지스터의 제조공정을 도시한 공정순서도.

Claims (16)

  1. 반도체기판의 제1절연막상에 형성되고 제1전도형의 불순물이 도우프된 제1도전층; 상기 제1도전층을 덮는 제2절연막; 상기 제1도전층상의 제2절연막에 형성된 콘택홀; 상기 콘택홀내에 노출된 상기 제1도전층, 콘택홀 내벽 및 상기 제2절연막의 소정부위에 형성된 반도체층; 상기 반도체층을 덮는 박막의 게이트절연막; 상기 콘택홀 및 상기 콘택홀의 입구주변부상에 오버랩되도록 상기 게이트절연막상에 형성된 제2도전층; 상기 콘택홀내의 상기 제1도전층과 접촉되는 상기 반도체층내에 상기 제1도전층내의 불순물이 상방향으로 확산되어 형성된 제1불순물영역; 상기 제2절연막상에 반도체층내에 상기 제2전도형의 불순물이 도우프된 제2불순물영역; 및 상기 제1 및 제2불순물영역들 사이에 한정되고 상기 콘택홀 내측벽상의 상기 반도체층으로 제공되는 채널영역을 구비한 것을 특징으로 하는 반도체 메모리장치의 박막트랜지스터.
  2. 제1항에 있어서, 상기 박막트랜지스터의 채널영역의 사이즈가 상기 콘택홀의 넓이 및 깊이로 설정되는 것을 특징으로 하는 반도체 메모리장치의 박막트랜지스터.
  3. 제1항에 있어서, 상기 제1불순물은 p형인 것을 특징으로 하는 반도체 메모리장치의 박막트랜지스터.
  4. 반도체 메모리장치의 박막트랜지스터의 제조방법에 있어서, 상기 박막트랜지스터의 제조공정이 다음 스텝들로 이루어진 것을 특징으로 하는 반도체 메모리장치의 박막트랜지스터의 제조방법. a. 반도체기판상의 제1절연막상에 제1전도형의 불순물이 도우프된 제1도전층의 패턴을 형성하는 공정; b. 상기 제1도전층의 패턴을 제2절연막으로 덮고 제1도전층상의 제2절연막에 콘택홀을 형성하는 공정; c. 상기 콘택홀내에 노출된 상기 제1도전층, 콘택홀 측벽 및 상기 제2절연막의 소정부위에 반도체층의 패턴을 형성하고, 이어서 상기 반도체층을 박막의 게이트절연막으로 덮는 공정; d. 상기 콘택홀 및 상기 콘택홀의 입구 주변부상에 오버랩되도록 상기 게이트절연막상에 제2도전층의 패턴을 형성하고, 상기 반도체층에 제1전도형의 불순물을 도핑하는 공정; e. 상기 불순물 도핑후 제2도전층의 패턴을 형성하기 위한 포토레지스트를 제거하는 공정.
  5. 제4항에 있어서, 상기 제1도전층은 p형 불순물이 도우프된 다결정실리콘인 것을 특징으로 하는 반도체 메모리장치의 박막트랜지스터의 제조방법.
  6. 제5항에 있어서, 상기 제1도전층은 p형 불순물이 도우프된 비정질실리콘인 것을 특징으로 하는 반도체 메모리장치의 박막트랜지스터의 제조방법.
  7. 제4항에 있어서, 상기 제1도전층의 불순물농도는 1×1013∼5×1015 /㎠인 것을 특징으로 하는 반도에 메모리장치의 박막트랜지스터의 제조방법.
  8. 제4항에 있어서, 상기 제2절연막의 두께는 2,000∼10,000Å인 것을 특징으로 하는 반도체 메모리장치의 박막트랜지스터의 제조방법.
  9. 제4항에 있어서, 상기 콘택홀의 직경은 0.2∼0.8㎛인 것을 특징으로 하는 반도체 메모리장치의 박막트랜지스터의 제조방법.
  10. 제4항에 있어서, 상기 반도체층은 두께 100∼1,500Å의 비정질실리콘인 것을 특징으로 하는 반도체 메모리장치의 박막트랜지스터의 제조방법.
  11. 제4항에 있어서, 상기 게이트절연막의 두께는 100∼1,000Å인 것을 특징으로 하는 반도체 메모리장치의 박막트랜지스터의 제조방법.
  12. 제4항에 있어서, 상기 제2도전층은 n형 불순물이 도우프된 다결정실리콘인 것은 특징으로 하는 반도체 메모리장치의 박막트랜지스터의 제조방법.
  13. 제4항에 있어서, 상기 반도체층의 불순물영역의 불순물 농도는 1×1013∼5×1015 /㎠인 것을 특징으로 하는 반도체 메모리장치의 박막트랜지스터의 제조방법.
  14. 제4항에 있어서, 상기 제2도전층은 p형 불순물이 도우프된 다결정실리콘인 것을 특징으로 하는 반도체 메모리장치의 박막트랜지스터의 제조방법.
  15. 제4항에 있어서, 상기 제2도전층은 비정질실리콘인 것을 특징으로 하는 반도체 메모리장치의 박막트랜지스터의 제조방법.
  16. 반도체 메모리장치의 박막트랜지스터의 제조방법에 있어서, 상기 박막트랜지스터의 제조공정이 다음 스텝들로 이루어진 것을 특징으로 하는 반도체 메모리장치의 박막트랜지스터의 제조방법. a. 반도체기판상의 제1절연막상에 제1전도형의 불순물이 도우프된 제1도전층의 패턴을 형성하는 공정; b. 상기 제1도전층의 패턴을 제2절연막으로 덮고 제1도전층상의 제2절연막에 콘택홀을 형성하는 공정; c. 상기 콘택홀내에 노출된 상기 제1도전층, 콘택홀 측벽 및 상기 제2절연막의 소정부위에 반도체층의 패턴을 형성하고, 이어서 상기 반도체층을 박막의 게이트절연막으로 덮는 공정; d. 상기 콘택홀 및 상기 콘택홀의 입구 주변부상에 오버랩되도록 상기 게이트절연막에 제2도전층의 패턴을 형성하는 공정; 및 e. 상기 패턴형성후, 포토레지스트를 덮고 포토레지스트에 개구를 형성하고 개구를 통해 상기 반도체층의 소정영역에 제1도전형이 불순물을 도핑하는 공정.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920006678A 1991-12-27 1992-04-21 반도체 메모리장치의 박막트랜지스터 및 그 제조방법 KR950001159B1 (ko)

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KR1019920006678A KR950001159B1 (ko) 1991-12-27 1992-04-21 반도체 메모리장치의 박막트랜지스터 및 그 제조방법
FR9207651A FR2685818B1 (fr) 1991-12-27 1992-06-23 Transistor a couches minces pour un dispositif formant memoire a semiconducteur et procede de fabrication de celui-ci.
GB9213809A GB2262838B (en) 1991-12-27 1992-06-29 Thin-film-transistor for semi-conductor memory device and fabricating method therefor
ITMI921603A IT1255398B (it) 1991-12-27 1992-06-30 Transistor a film sottile per dispositivo di memoria a semiconduttore e suo procedimento di fabbricazione.
US07/906,369 US5270968A (en) 1991-12-27 1992-06-30 Thin-film transistor for semiconductor memory device and fabricating method thereof
DE4221420A DE4221420A1 (de) 1991-12-27 1992-06-30 Duennschichttransistor fuer ein halbleiterspeicherbauelement und verfahren zu dessen herstellung
TW081105179A TW212851B (ko) 1991-12-27 1992-06-30
CN92105269A CN1032286C (zh) 1991-12-27 1992-06-30 用于半导体存储器件的薄膜晶体管及其制造方法
JP4187031A JPH0773114B2 (ja) 1991-12-27 1992-07-14 半導体メモリ装置の薄膜トランジスタおよびその製造方法

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KR91-24664 1991-12-27
KR910024664 1991-12-27
KR1019920006678A KR950001159B1 (ko) 1991-12-27 1992-04-21 반도체 메모리장치의 박막트랜지스터 및 그 제조방법

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CN1073806A (zh) 1993-06-30
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JPH0653440A (ja) 1994-02-25
IT1255398B (it) 1995-10-31
JPH0773114B2 (ja) 1995-08-02
US5270968A (en) 1993-12-14
DE4221420A1 (de) 1993-07-01
CN1032286C (zh) 1996-07-10
KR950001159B1 (ko) 1995-02-11
FR2685818A1 (fr) 1993-07-02
GB9213809D0 (en) 1992-08-12
ITMI921603A0 (it) 1992-06-30
GB2262838A (en) 1993-06-30
GB2262838B (en) 1995-09-06

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