CN1032286C - 用于半导体存储器件的薄膜晶体管及其制造方法 - Google Patents

用于半导体存储器件的薄膜晶体管及其制造方法 Download PDF

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CN1032286C
CN1032286C CN92105269A CN92105269A CN1032286C CN 1032286 C CN1032286 C CN 1032286C CN 92105269 A CN92105269 A CN 92105269A CN 92105269 A CN92105269 A CN 92105269A CN 1032286 C CN1032286 C CN 1032286C
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金长来
金汉洙
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Samsung Electronics Co Ltd
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Abstract

用于半导体存储器件的TFT，包括第一绝缘层1上形成的第一导电层2、覆盖在其上的第二绝缘层3，第二绝缘层内形成的开口4，在开口4中暴露第一导电层的表面及在第二绝缘层3上预定部分表面形成半导体层5，覆盖在半导体层5上的薄栅极绝缘层6，在其上形成第二导电层7，在半导体层5之第一部分内形成的第一杂质区，在半导体层5之第二部分内形成的第二杂质区，和在半导体层5内第一与第二杂质区间所确定的沟道区5c。

Description

用于半导体存储器件的薄膜晶体管及其制造方法
本发明涉及一种用于半导体存储器件的薄膜晶体管(TFT)及其制造方法，特别是涉及具有六晶体管存储单元结构和一个静态随机存储器(SRAM)的PMOS TFT晶体管及其制造方法。
由于近来对SRAM的需要不断增长和DRAM价格的不稳定，半导体存储器件制造商曾做出努力，利用动态随机存储器件(DRAM)批量生产线来增加静态随机存储器(SRAM)的产量。对SRAM需求的不断增长是因为它们具有独一无二的特性，如高速、低功耗、无刷新要求以及简化的系统设计，还由于向多功能、高质量、小型化和重量轻系统发展的趋势。然而，由于SRAM具有比DRAM复杂的单元结构，SRAM的密度落后了一代。
目前的SRAM分为四晶体管和六晶体管存储单元结构。四晶体管型在容量方面领先，它由一个NMOS型存储单元和CMOS型外围电路组成，NMOS型存储单元有一个多晶硅作为高阻负载。由于芯片尺寸的原因，最初生产的是256Kb SRAM，没有考虑具有全CMOS结构的低功耗SRAM。因此，最近采用一种叠层型TFT来降低功耗，并保持和传统的四晶体管型(《VLSI技术论文集》1990年版，第19至24页)芯片同样大小，这样叠层型TFT将高阻多晶硅负载改为PMOS。
不过，传统TFT的源极、漏极和沟道区都以二维平面结构来排列，占用了很大的面积。相应地，二维结构的TFT影响了SRAM的高密度和大容量。
本发明的目的是提供用于半导体存储器件的一种三维TFT。
本发明的另一个目的是提供制造上述TFT最适宜的方法。
为了达到本发明的第一个目的，这里提供了一种TFT，包括：
第一导电层，它在第一绝缘层上形成并用第一导电型杂质掺杂；
第二绝缘层，它覆盖在第一导电层上；
一个开口，它在第一导电层上的第二绝缘层内形成；
一个半导体层，它在暴露于开口内的第一导电层的表面和第二绝缘层的预定部分的表面上形成；
一个薄栅极绝缘层，它覆盖在半导体层上；
第二导电层，它在开口里面和周围的薄栅极绝缘层上形成；
第一杂质区，它在与开口底部的掺杂有第一导电型杂质的第一导电层接触的半导体层的第一部分内形成；
第二杂质区，它在第二绝缘层上的半导体层的第二部分内形成，并用第一导电型杂质掺杂；以及
一个沟道区，它处在半导体层内的第一与第二杂质层之间。
为了达到本发明的另一个目的，根据本发明的TFT通过以下步骤制造：
在第一绝缘层上形成用第一导电型杂质掺杂的第一导电层；
用第二绝缘层覆盖第一导电层；
在第一导电层上的第二绝缘层内形成一个开口；
在暴露于开口内的第一导电层的表面和第二绝缘层的预定部分的表面上形成一个半导体层；
用薄栅极绝缘层覆盖半导体并同时通过第一导电层内杂质的向上扩散，在与暴露的第一导电层接触的半导体层的第一部分内形成第一杂质区；
在开口里面和周围的薄栅极绝缘层上形成第二导电层；以及
通过掺杂工艺在半导体层的第二部分形成第二杂质区，它不盖第二绝缘层上的第二导电层。
通过参照附图来详细说明本发明的一个最佳实施例，本发明的上述目的以及其它优点就会更加明显，这些图是；
图1A为用于半导体存储器件的一个传统的TFT的平面布局图；
图1B为沿图1A所示a—a线所取的TFT的剖面图；
图2A为本发明的用于半导体存储器件的TFT的平面布局图；
图2B为沿图2A所示a—a线所取的TFT的剖面图；
图3A至3E展示了本发明的用于半导体存储器件的TFT的制造过程。
在说明本发明的实施例前，应先说明一下用于传统的半导体存储器件的TFT。
参照图1A和1B，传统上，在第一绝缘层1上形成多晶硅的第一导电层2的一个图形，作为PMOS TFT的一个漏极接点，然后形成第二绝缘层3。在第二绝缘层3上形成一个开口，即一个通过口或接触口4之后，淀积上非晶硅半导体层5，然后按图形加工。在半导体层5上形成TFT栅极绝缘层6之后，在栅极绝缘层6上淀积多晶硅第二导电层7，然后按图形加工。这样，就形成了TFT的一个栅极电极，与在第二绝缘层3上一个预定区域内的半导体层5重叠。接着，在半导体层5没有被第二导电层7重叠的那部分离子注入或离子射入P型杂质，自我调整，从而形成PMOS TFT的源极和漏极区5a和5b。源极和漏极区5a和5b之间的半导体层作为PMOSTFT的一个沟道区5c。这样，由于为在一个二维平面上形成作为一个传统SRAM负载的PMOS TFT，就应分配一个预定区域，它阻碍了SRAM实现高密度和大容量。
因此，在本发明中，为了减小SRAM的PMOS TFT所占的面积，使用了三维结构。图2A为根据本发明的一个三维TFT的平面布局图，图2B为沿图2A中a—a线所取的一个剖面图。本发明与先有技术的区别在于在PMOS TFT的漏极接触孔内壁上形成的半导体层用作沟道区5c，在接触孔4底部形成的半导体层用作源极区5a。作为栅极的第二导电层7形成的图形还复盖接触孔。并且，通过P型杂质向上扩散来形成源极区5a，即在第一导电层2内置入的第一导电杂质作为源极接点。根据上述结构，PMOS TFT的沟道大小可以调整至接触孔的直径或深度。因此，与传统的PMOSTFT所占的面积相比，面积减小了约40％，而且布线的自由度也大大改善了。
根据本发明的TFT最佳实施例的制造方法由图3A至3E所示的步骤组成。
参照图3A，在一个半导体基片(未示出)上平面化的第一绝缘层1上淀积500至2,000_厚的第一导电层2(例如，多晶硅或非晶硅)。然后，离子注入或射入P型杂质，浓度为1×1013～5×1015/cm2，接着，用普通的光刻法形成第一导电层2的图形。
参照图3B，在第一导电层2的图形上形成2,000至10,000_厚的第二绝缘层3。接着，用普通的光刻法在第一导电层2上的第二绝缘层3内形成一个直径为0.2至0.8μm的接触孔，将第一导电层2暴露出来。
参照图3C，在其中形成了接触孔4的第二绝缘层3上淀积100至1,000_厚的非晶硅半导体层5，然后用普通的光刻法形成半导体层5的图形。接着，用化学汽相淀积法在半导体层5上作为氧化物层涂敷上同样厚度(100到1,000_)的栅极绝缘层6，此时，P型杂质自第一导电层2向上扩散至半导体层5，这样，在半导体层5内形成一个P型杂质区，即源极区5a，并与第一导电层2相接触。
参照图3D，在栅极绝缘层6上淀积500至2,000_厚的第二导电层7(例如，多晶硅或非晶硅)，然后，将n型或P型杂质掺入第二导电层7，浓度为1×1014～1×1016/cm2，用普通的光刻法形成第二导电层7的图形，作为栅极电极。在去除用以形成第二导电层7图形的光致抗蚀剂8之前，向半导体层5未被第二导电层7重叠的那部分离子注入或射入P型杂质，浓度为1×1013～5×1015/cm2，从而形成一个P型杂质区，即漏极区5b。否则，会如图3D—1所示，在光致抗蚀剂8去除后，形成光致抗蚀剂8a，然后在其内形成一个开口8b。然后，通过开口8b，在半导体层5的预定区域内形成P型杂质区5b′。
参照图3e，去除光致抗蚀剂(8或8a)后，PMOS TFT就完成了。上述PMOS TFT的沟道区5c是作为接触孔4内壁上形成的半导体层和作为未因第二导电层7的图形而注入P型杂质的半导体层来提供的。
如上所述，本发明有一个非晶硅PMOS TFT负载的SRAM的，通过重叠PMOS TFT的源极接触区和作为栅极的第二导电层，接触孔边壁上的半导体层可用作沟道区以形成三维TFT，这样减少了TFT所占用的面积，从而提高了SRAM的密度和容量以及布线的自由度。
尽管参照最佳实施例来具体地展示和说明了本发明，但本领域的技术人员应懂得，在不背离权利要求书所规定的本发明的精神和范围的前提下，可以对其在形式上和细节上做各种不同的改变。

Claims (18)

1.一种用于半导体存储器件的TFT，其特征在于包括：
第一导电层2，它在第一绝缘层1上形成并用第一导电型杂质掺杂；
第二绝缘层3，它覆盖在所说第一导电层2上；
一个开口4，它在所说的第一导电层2上的第二绝缘层3内形成；
一个半导体层5，它在暴露于所说的开口4内的所说的第一导电层2的表面和所说的第二绝缘层3的预定部分的表面上形成；
一个薄栅极绝缘层6，它覆盖在所说的半导体层5上；
第二导电层7，它在所说的开口4里面及其周围的薄栅极绝缘层6上形成；
第一杂质区，它在与所说开口4底部的第一导电层2接触的所说半导体层5的第一部分内形成，并用第一导电型杂质掺杂；
第二杂质区，它在所说第二绝缘层3上的半导体层5的第二部分内形成，并用第一导电型杂质掺杂；以及
一个沟道区5c，它处在所说的半导体层5内的第一与第二杂质区之间。
2.如权利要求1所说的一种用于半导体存储器件的TFT，其特征在于所说的沟道区5c的大小由所说开口4的直径或深度来决定。
3.如权利要求1所说的一种用于半导体存储器件的TFT，其特征在于所说的第一导电型杂质为P型。
4.如权利要求1所说的一种用于半导体存储器件的TFT，其特征在于所说的第一杂质区的杂质自所说的第一导电层2向上扩散。
5.一种用于半导体存储器件的TFT的制造方法，其特征在于包括以下步骤：
在第一绝缘层1上形成用第一导电型杂质掺杂的第一导电层2；
用第二绝缘层3覆盖所说的第一导电层2；
在所说的第一导电层2上的第二绝缘层3内形成一个开口4；
在暴露于所说开口4内的第一导电层2的表面和所说第二绝缘层3的预定部分的表面上形成一个半导体层5；
用薄栅极绝缘层6覆盖所说的半导体层5，并同时通过向上扩散所说第一导电层2内的杂质，在与所说暴露的第一导电层2接触的半导体层5的第一部分内形成第一杂质区；
在所说的开口4里面和周围的薄栅极绝缘层6上形成第二导电层7；以及
通过掺杂工艺在所说半导体层5的第二部分形成第二杂质区，它不盖所说第二绝缘层3上的第二导电层7。
6.如权利要求5所说的一种用于半导体存储器件的TFT的制造方法，其特征在于所说的第一导电层2为掺有P型杂质的多晶硅。
7.如权利要求5所说的一种用于半导体存储器件的TFT的制造方法，其特征在于所说的第一导电层2为掺有P型杂质的非晶硅。
8.如权利要求5所说的一种用于半导体存储器件TFT的制造方法，其特征在于所说第一导电层2的杂质浓度为1×1013～5×1015/cm2。
9.如权利要求5所说的一种用于半导体存储器件的TFT的制造方法，其特征在于所说的第二绝缘层3的厚度为2,000至10,000_。
10.如权利要求5所说的一种用于半导体存储器件的TFT的制造方法，其特征在于所说的开口4的直径为0.2～0.8μm。
11.如权利要求5所说的一种用于半导体存储器件的TFT的制造方法，其特征在于所说的半导体层5为100至1,500_厚，并由非晶硅制成。
12.如权利要求5所说的一种用于半导体存储器件TFT的制造方法，其特征在于所说的栅极绝缘层6的厚度为100至1,000_。
13.如权利要求5所说的一种用于半导体存储器件的TFT的制造方法，其特征在于所说的第二导电层7为掺有n型杂质的多晶硅。
14.如权利要求5所说的一种用于半导体存储器件的TFT的制造方法，其特征在于所说半导体层5中的杂质区的杂质浓度为1×1013～5×1015/cm/2。
15.如权利要求5所说的一种用于半导体存储器件的TFT的制造方法，其特征在于所说的第二导电层7为掺有P型杂质的多晶硅。
16.如权利要求5所说的一种用于半导体存储器件的TFT的制造方法，其特征在于所说的第二导电层7为非晶硅。
17.如权利要求5所说的一种用于半导体存储器件的TFT的制造方法，其特征在于所说的掺杂过程是用所说的第二导电层7作为掩模进行离子注入。
18.如权利要求5所说的一种用于半导体存储器件的TFT的制造方法，其特征在于所说的掺杂过程是用一个预定的光致抗蚀剂图形作为掩模进行离子注入。
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