KR930014852A - 반도체 집적 회로 장치의 제조 방법, 그것에 사용되는 성형장치 및 성형 재료 - Google Patents

반도체 집적 회로 장치의 제조 방법, 그것에 사용되는 성형장치 및 성형 재료 Download PDF

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Publication number
KR930014852A
KR930014852A KR1019920025180A KR920025180A KR930014852A KR 930014852 A KR930014852 A KR 930014852A KR 1019920025180 A KR1019920025180 A KR 1019920025180A KR 920025180 A KR920025180 A KR 920025180A KR 930014852 A KR930014852 A KR 930014852A
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KR
South Korea
Prior art keywords
molding material
cavity
integrated circuit
circuit device
molding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1019920025180A
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English (en)
Korean (ko)
Inventor
가쯔오 아라이
스미오 오까다
다까시 오바
가즈야 다까하시
마유미 가네꼬
Original Assignee
가나이 쯔또무
가부시끼가이샤 히다찌세이사꾸쇼
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Filing date
Publication date
Application filed by 가나이 쯔또무, 가부시끼가이샤 히다찌세이사꾸쇼 filed Critical 가나이 쯔또무
Publication of KR930014852A publication Critical patent/KR930014852A/ko
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
KR1019920025180A 1991-12-25 1992-12-23 반도체 집적 회로 장치의 제조 방법, 그것에 사용되는 성형장치 및 성형 재료 Withdrawn KR930014852A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3357062A JP3059560B2 (ja) 1991-12-25 1991-12-25 半導体装置の製造方法およびそれに使用される成形材料
JP91-357062 1991-12-25

Publications (1)

Publication Number Publication Date
KR930014852A true KR930014852A (ko) 1993-07-23

Family

ID=18452192

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920025180A Withdrawn KR930014852A (ko) 1991-12-25 1992-12-23 반도체 집적 회로 장치의 제조 방법, 그것에 사용되는 성형장치 및 성형 재료

Country Status (4)

Country Link
US (1) US5304512A (enExample)
JP (1) JP3059560B2 (enExample)
KR (1) KR930014852A (enExample)
TW (1) TW226483B (enExample)

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JP3057130B2 (ja) 1993-02-18 2000-06-26 三菱電機株式会社 樹脂封止型半導体パッケージおよびその製造方法
JP2994171B2 (ja) * 1993-05-11 1999-12-27 株式会社東芝 半導体装置の製造方法および封止用部材の製造方法
US6232152B1 (en) 1994-05-19 2001-05-15 Tessera, Inc. Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures
US5776796A (en) * 1994-05-19 1998-07-07 Tessera, Inc. Method of encapsulating a semiconductor package
US5663106A (en) * 1994-05-19 1997-09-02 Tessera, Inc. Method of encapsulating die and chip carrier
US5834339A (en) 1996-03-07 1998-11-10 Tessera, Inc. Methods for providing void-free layers for semiconductor assemblies
US6359335B1 (en) 1994-05-19 2002-03-19 Tessera, Inc. Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures
JP2994219B2 (ja) 1994-05-24 1999-12-27 シャープ株式会社 半導体デバイスの製造方法
DE4428808C2 (de) * 1994-08-13 2003-07-17 Bosch Gmbh Robert Verfahren zur Herstellung eines Bauelementes nach dem Anodic-Bonding-Verfahren und Bauelement
JP3199963B2 (ja) * 1994-10-06 2001-08-20 株式会社東芝 半導体装置の製造方法
US5929517A (en) 1994-12-29 1999-07-27 Tessera, Inc. Compliant integrated circuit package and method of fabricating the same
US5951813A (en) * 1996-05-02 1999-09-14 Raytheon Company Top of die chip-on-board encapsulation
JP2871591B2 (ja) * 1996-05-14 1999-03-17 日本電気株式会社 高周波用電子部品および高周波用電子部品の製造方法
US5656549A (en) * 1996-08-19 1997-08-12 Motorola, Inc. Method of packaging a semiconductor device
JPH11121488A (ja) * 1997-10-15 1999-04-30 Toshiba Corp 半導体装置の製造方法及び樹脂封止装置
WO1999023700A1 (en) 1997-11-05 1999-05-14 Martin Robert A Chip housing, methods of making same and methods for mounting chips therein
JP3132449B2 (ja) * 1998-01-09 2001-02-05 日本電気株式会社 樹脂外装型半導体装置の製造方法
JP3486557B2 (ja) 1998-07-30 2004-01-13 宮崎沖電気株式会社 トランスファ成形装置及び半導体装置の製造方法
US6214640B1 (en) 1999-02-10 2001-04-10 Tessera, Inc. Method of manufacturing a plurality of semiconductor packages
SG92685A1 (en) * 1999-03-10 2002-11-19 Towa Corp Method of coating semiconductor wafer with resin and mold used therefor
US6576496B1 (en) * 2000-08-21 2003-06-10 Micron Technology, Inc. Method and apparatus for encapsulating a multi-chip substrate array
JP3711333B2 (ja) * 2001-07-27 2005-11-02 沖電気工業株式会社 半導体装置の製造方法および樹脂封止装置
US7335995B2 (en) * 2001-10-09 2008-02-26 Tessera, Inc. Microelectronic assembly having array including passive elements and interconnects
US6897565B2 (en) * 2001-10-09 2005-05-24 Tessera, Inc. Stacked packages
US6977440B2 (en) * 2001-10-09 2005-12-20 Tessera, Inc. Stacked packages
TW548816B (en) * 2002-01-23 2003-08-21 Via Tech Inc Formation method of conductor pillar
JP4519398B2 (ja) * 2002-11-26 2010-08-04 Ｔｏｗａ株式会社 樹脂封止方法及び半導体装置の製造方法
KR100510517B1 (ko) * 2003-01-29 2005-08-26 삼성전자주식회사 보호캡을 가지는 플립칩 패키지의 제조 방법
JP4794354B2 (ja) * 2006-05-23 2011-10-19 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
US7961470B2 (en) * 2006-07-19 2011-06-14 Infineon Technologies Ag Power amplifier
JP2009099905A (ja) * 2007-10-19 2009-05-07 Rohm Co Ltd 半導体装置
US8084301B2 (en) * 2008-09-11 2011-12-27 Sanyo Electric Co., Ltd. Resin sheet, circuit device and method of manufacturing the same
JP5542318B2 (ja) * 2008-09-29 2014-07-09 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 樹脂シートおよびそれを用いた回路装置の製造方法
JP4929382B2 (ja) * 2010-07-13 2012-05-09 株式会社東芝 電子部品構造体及び電子機器
KR101259844B1 (ko) * 2011-01-31 2013-05-03 엘지이노텍 주식회사 리드 크랙이 강화된 전자소자용 탭 테이프 및 그의 제조 방법
JP6057824B2 (ja) * 2013-04-19 2017-01-11 Ｔｏｗａ株式会社 電子部品の圧縮樹脂封止方法及び圧縮樹脂封止装置
CN104022145B (zh) * 2014-06-23 2017-01-25 深圳市华星光电技术有限公司 基板的封装方法及封装结构
US20180117813A1 (en) * 2016-11-02 2018-05-03 Asm Technology Singapore Pte Ltd Molding apparatus including a compressible structure
KR102687751B1 (ko) * 2019-07-15 2024-07-23 에스케이하이닉스 주식회사 브리지 다이를 포함한 반도체 패키지
CN112432539B (zh) * 2020-12-03 2025-01-24 浙江银轮机械股份有限公司 多级中冷器及其水路隔离件和水路隔离组件

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JPS57148360A (en) * 1981-03-09 1982-09-13 Seiko Keiyo Kogyo Kk Semiconductor device
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JPS58122757A (ja) * 1982-01-18 1983-07-21 Seiko Keiyo Kogyo Kk 樹脂モ−ルド半導体装置
JPS58165333A (ja) * 1982-03-26 1983-09-30 Toshiba Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
JP3059560B2 (ja) 2000-07-04
US5304512A (en) 1994-04-19
TW226483B (enExample) 1994-07-11
JPH05175264A (ja) 1993-07-13

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