TW226483B - - Google Patents

Info

Publication number
TW226483B
TW226483B TW081109119A TW81109119A TW226483B TW 226483 B TW226483 B TW 226483B TW 081109119 A TW081109119 A TW 081109119A TW 81109119 A TW81109119 A TW 81109119A TW 226483 B TW226483 B TW 226483B
Authority
TW
Taiwan
Application number
TW081109119A
Original Assignee
Hitachi Seisakusyo Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Seisakusyo Kk filed Critical Hitachi Seisakusyo Kk
Application granted granted Critical
Publication of TW226483B publication Critical patent/TW226483B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device
TW081109119A 1991-12-25 1992-11-14 TW226483B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3357062A JP3059560B2 (ja) 1991-12-25 1991-12-25 半導体装置の製造方法およびそれに使用される成形材料

Publications (1)

Publication Number Publication Date
TW226483B true TW226483B (zh) 1994-07-11

Family

ID=18452192

Family Applications (1)

Application Number Title Priority Date Filing Date
TW081109119A TW226483B (zh) 1991-12-25 1992-11-14

Country Status (4)

Country Link
US (1) US5304512A (zh)
JP (1) JP3059560B2 (zh)
KR (1) KR930014852A (zh)
TW (1) TW226483B (zh)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3057130B2 (ja) * 1993-02-18 2000-06-26 三菱電機株式会社 樹脂封止型半導体パッケージおよびその製造方法
JP2994171B2 (ja) * 1993-05-11 1999-12-27 株式会社東芝 半導体装置の製造方法および封止用部材の製造方法
US5834339A (en) 1996-03-07 1998-11-10 Tessera, Inc. Methods for providing void-free layers for semiconductor assemblies
US6359335B1 (en) 1994-05-19 2002-03-19 Tessera, Inc. Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures
US5663106A (en) * 1994-05-19 1997-09-02 Tessera, Inc. Method of encapsulating die and chip carrier
US5776796A (en) * 1994-05-19 1998-07-07 Tessera, Inc. Method of encapsulating a semiconductor package
US6232152B1 (en) 1994-05-19 2001-05-15 Tessera, Inc. Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures
DE4428808C2 (de) * 1994-08-13 2003-07-17 Bosch Gmbh Robert Verfahren zur Herstellung eines Bauelementes nach dem Anodic-Bonding-Verfahren und Bauelement
JP3199963B2 (ja) * 1994-10-06 2001-08-20 株式会社東芝 半導体装置の製造方法
US5929517A (en) 1994-12-29 1999-07-27 Tessera, Inc. Compliant integrated circuit package and method of fabricating the same
US5951813A (en) * 1996-05-02 1999-09-14 Raytheon Company Top of die chip-on-board encapsulation
JP2871591B2 (ja) * 1996-05-14 1999-03-17 日本電気株式会社 高周波用電子部品および高周波用電子部品の製造方法
US5656549A (en) * 1996-08-19 1997-08-12 Motorola, Inc. Method of packaging a semiconductor device
JPH11121488A (ja) * 1997-10-15 1999-04-30 Toshiba Corp 半導体装置の製造方法及び樹脂封止装置
WO1999023700A1 (en) 1997-11-05 1999-05-14 Martin Robert A Chip housing, methods of making same and methods for mounting chips therein
JP3132449B2 (ja) * 1998-01-09 2001-02-05 日本電気株式会社 樹脂外装型半導体装置の製造方法
JP3486557B2 (ja) 1998-07-30 2004-01-13 宮崎沖電気株式会社 トランスファ成形装置及び半導体装置の製造方法
US6214640B1 (en) 1999-02-10 2001-04-10 Tessera, Inc. Method of manufacturing a plurality of semiconductor packages
SG92685A1 (en) * 1999-03-10 2002-11-19 Towa Corp Method of coating semiconductor wafer with resin and mold used therefor
US6576496B1 (en) 2000-08-21 2003-06-10 Micron Technology, Inc. Method and apparatus for encapsulating a multi-chip substrate array
JP3711333B2 (ja) * 2001-07-27 2005-11-02 沖電気工業株式会社 半導体装置の製造方法および樹脂封止装置
DE10297316T5 (de) * 2001-10-09 2004-12-09 Tessera, Inc., San Jose Gestapelte Baugruppen
US6977440B2 (en) * 2001-10-09 2005-12-20 Tessera, Inc. Stacked packages
US7335995B2 (en) * 2001-10-09 2008-02-26 Tessera, Inc. Microelectronic assembly having array including passive elements and interconnects
TW548816B (en) * 2002-01-23 2003-08-21 Via Tech Inc Formation method of conductor pillar
JP4519398B2 (ja) * 2002-11-26 2010-08-04 Ｔｏｗａ株式会社 樹脂封止方法及び半導体装置の製造方法
KR100510517B1 (ko) * 2003-01-29 2005-08-26 삼성전자주식회사 보호캡을 가지는 플립칩 패키지의 제조 방법
JP4794354B2 (ja) * 2006-05-23 2011-10-19 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
US7961470B2 (en) * 2006-07-19 2011-06-14 Infineon Technologies Ag Power amplifier
JP2009099905A (ja) * 2007-10-19 2009-05-07 Rohm Co Ltd 半導体装置
JP5542318B2 (ja) * 2008-09-29 2014-07-09 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 樹脂シートおよびそれを用いた回路装置の製造方法
US8084301B2 (en) * 2008-09-11 2011-12-27 Sanyo Electric Co., Ltd. Resin sheet, circuit device and method of manufacturing the same
JP4929382B2 (ja) * 2010-07-13 2012-05-09 株式会社東芝 電子部品構造体及び電子機器
KR101259844B1 (ko) 2011-01-31 2013-05-03 엘지이노텍 주식회사 리드 크랙이 강화된 전자소자용 탭 테이프 및 그의 제조 방법
JP6057824B2 (ja) * 2013-04-19 2017-01-11 Ｔｏｗａ株式会社 電子部品の圧縮樹脂封止方法及び圧縮樹脂封止装置
CN104022145B (zh) * 2014-06-23 2017-01-25 深圳市华星光电技术有限公司 基板的封装方法及封装结构
US20180117813A1 (en) * 2016-11-02 2018-05-03 Asm Technology Singapore Pte Ltd Molding apparatus including a compressible structure

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5739558A (en) * 1980-08-20 1982-03-04 Citizen Watch Co Ltd Resin sealing method for ic
JPS57148360A (en) * 1981-03-09 1982-09-13 Seiko Keiyo Kogyo Kk Semiconductor device
JPS5818931A (ja) * 1981-07-28 1983-02-03 Citizen Watch Co Ltd Ｉｃの封止方法
JPS58122757A (ja) * 1982-01-18 1983-07-21 Seiko Keiyo Kogyo Kk 樹脂モ−ルド半導体装置
JPS58165333A (ja) * 1982-03-26 1983-09-30 Toshiba Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
US5304512A (en) 1994-04-19
KR930014852A (ko) 1993-07-23
JPH05175264A (ja) 1993-07-13
JP3059560B2 (ja) 2000-07-04

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