JPS57148360A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS57148360A
JPS57148360A JP3361081A JP3361081A JPS57148360A JP S57148360 A JPS57148360 A JP S57148360A JP 3361081 A JP3361081 A JP 3361081A JP 3361081 A JP3361081 A JP 3361081A JP S57148360 A JPS57148360 A JP S57148360A
Authority
JP
Japan
Prior art keywords
pellet
resin
chip
aperture
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3361081A
Other languages
Japanese (ja)
Inventor
Taiji Sato
Hironori Ando
Takayuki Kimura
Norio Terui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SEIKO KEIYO KOGYO KK
SEIKOO KEIYO KOGYO KK
SEIKOO KEIYOU KOGYO KK
Original Assignee
SEIKO KEIYO KOGYO KK
SEIKOO KEIYO KOGYO KK
SEIKOO KEIYOU KOGYO KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SEIKO KEIYO KOGYO KK, SEIKOO KEIYO KOGYO KK, SEIKOO KEIYOU KOGYO KK filed Critical SEIKO KEIYO KOGYO KK
Priority to JP3361081A priority Critical patent/JPS57148360A/en
Publication of JPS57148360A publication Critical patent/JPS57148360A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Abstract

PURPOSE:To obtain the reliable resin sealing for the subject semiconductor device by a method wherein the bump of a semiconductor chip is adhered to the terminal part of the conductive pattern provided on the lower surface of a flexible film, a resin pellet is inserted in the aperture of the pattern while the pellet is surrounded by a film reinforcing plate, the pellet is fused, and the surface of the chip is filled up with resin using a capillary phenomenon. CONSTITUTION:A conductive pattern 2 with a prescribed aperture is coated on the lower surface of the flexible film 1, a bump 4 which provided on the semiconductor chip 3 is adhered to the terminal part of the aperture. Then, a resin pellet 6 is placed on the aperture section of the pattern 2, and a film reinforcing plate 5 is provided on the film 1 in such a manner that the pellet is surrounded maintaining a prescribed clearance. Subsequently, the pellet 6 is fused by heating, the pellet 6 is gelatinized by the reinforcing plate 5 which serves as a heat source too, and resin is filled on the chip 3 utilizing the capillary phenomenon generating between the chip 3 and the pattern 2. Accordingly, a reliable resin sealing can be obtained, and an automatic operation can also be performed.
JP3361081A 1981-03-09 1981-03-09 Semiconductor device Pending JPS57148360A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3361081A JPS57148360A (en) 1981-03-09 1981-03-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3361081A JPS57148360A (en) 1981-03-09 1981-03-09 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS57148360A true JPS57148360A (en) 1982-09-13

Family

ID=12391224

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3361081A Pending JPS57148360A (en) 1981-03-09 1981-03-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57148360A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02260445A (en) * 1989-03-30 1990-10-23 Matsushita Electric Ind Co Ltd Ic package
US5304512A (en) * 1991-12-25 1994-04-19 Hitachi, Ltd. Process for manufacturing semiconductor integrated circuit device, and molding apparatus and molding material for the process
KR100261959B1 (en) * 1996-02-01 2000-07-15 포만 제프리 엘 Electronic package with strain relief means and method of making

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02260445A (en) * 1989-03-30 1990-10-23 Matsushita Electric Ind Co Ltd Ic package
US5304512A (en) * 1991-12-25 1994-04-19 Hitachi, Ltd. Process for manufacturing semiconductor integrated circuit device, and molding apparatus and molding material for the process
KR100261959B1 (en) * 1996-02-01 2000-07-15 포만 제프리 엘 Electronic package with strain relief means and method of making

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