JPS6472547A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS6472547A
JPS6472547A JP62229297A JP22929787A JPS6472547A JP S6472547 A JPS6472547 A JP S6472547A JP 62229297 A JP62229297 A JP 62229297A JP 22929787 A JP22929787 A JP 22929787A JP S6472547 A JPS6472547 A JP S6472547A
Authority
JP
Japan
Prior art keywords
chip
face
temperature
substrate
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62229297A
Other languages
Japanese (ja)
Inventor
Kimiya Ichikawa
Masabumi Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP62229297A priority Critical patent/JPS6472547A/en
Publication of JPS6472547A publication Critical patent/JPS6472547A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To obtain a semiconductor device having excellent reliability and a small size by providing a resin layer filled between a circuit substrate and the face of a face-down bonded semiconductor chip so as to substantially expose the rear face of the chip. CONSTITUTION:A resin layer 31 filled between a circuit substrate 13 and the face of a semiconductor chip 15 is so provided as to substantially expose the rear face 15b of the chip 15 in a semiconductor device in which the chip 15 is face-down bonded on the substrate 13. After the chip 15 is face-down bonded to the substrate 13, and the periphery of the chip 15 on the substrate 13 is coated at a first temperature with resin 31 which exhibits a first viscosity at the first temperature and a viscosity lower than the first viscosity at a second temperature higher than the first temperature. Then, the substrate 13 coated with the resin 31 is allowed to stand for at the second temperature. The resin 31 is cured at the temperature higher than the second temperature, and a semiconductor device is manufactured.
JP62229297A 1987-09-12 1987-09-12 Semiconductor device and manufacture thereof Pending JPS6472547A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62229297A JPS6472547A (en) 1987-09-12 1987-09-12 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62229297A JPS6472547A (en) 1987-09-12 1987-09-12 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS6472547A true JPS6472547A (en) 1989-03-17

Family

ID=16889928

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62229297A Pending JPS6472547A (en) 1987-09-12 1987-09-12 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS6472547A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5670826A (en) * 1993-09-29 1997-09-23 Matsushita Electric Industrial Co., Ltd. Method for mounting a semiconductor device on a circuit board using a conductive adhesive and a thermosetting resin, and a circuit board with a semiconductor device mounted thereon using the method
US6018188A (en) * 1997-03-28 2000-01-25 Nec Corporation Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5670826A (en) * 1993-09-29 1997-09-23 Matsushita Electric Industrial Co., Ltd. Method for mounting a semiconductor device on a circuit board using a conductive adhesive and a thermosetting resin, and a circuit board with a semiconductor device mounted thereon using the method
US6018188A (en) * 1997-03-28 2000-01-25 Nec Corporation Semiconductor device

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