JPS5314564A - Bonding method of s# chip and substrate - Google Patents

Bonding method of s# chip and substrate

Info

Publication number
JPS5314564A
JPS5314564A JP8823176A JP8823176A JPS5314564A JP S5314564 A JPS5314564 A JP S5314564A JP 8823176 A JP8823176 A JP 8823176A JP 8823176 A JP8823176 A JP 8823176A JP S5314564 A JPS5314564 A JP S5314564A
Authority
JP
Japan
Prior art keywords
substrate
chip
bonding method
providing
dummy terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8823176A
Other languages
Japanese (ja)
Other versions
JPS5923109B2 (en
Inventor
Tasao Soga
Tomiro Yasuda
Kazuya Takahashi
Kozo Odawara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8823176A priority Critical patent/JPS5923109B2/en
Publication of JPS5314564A publication Critical patent/JPS5314564A/en
Publication of JPS5923109B2 publication Critical patent/JPS5923109B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: To reduce the temperature rise during operating by providing dummy terminals on the insulation layer of a Si substrate surface thereby increasing the reliability of strength resistance and temperature resistance cycles and providing a cooling plate on the rear of the substrate and connecting said plate to the dummy terminals.
COPYRIGHT: (C)1978,JPO&Japio
JP8823176A 1976-07-26 1976-07-26 Connection method between Si chip and wiring board Expired JPS5923109B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8823176A JPS5923109B2 (en) 1976-07-26 1976-07-26 Connection method between Si chip and wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8823176A JPS5923109B2 (en) 1976-07-26 1976-07-26 Connection method between Si chip and wiring board

Publications (2)

Publication Number Publication Date
JPS5314564A true JPS5314564A (en) 1978-02-09
JPS5923109B2 JPS5923109B2 (en) 1984-05-30

Family

ID=13937082

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8823176A Expired JPS5923109B2 (en) 1976-07-26 1976-07-26 Connection method between Si chip and wiring board

Country Status (1)

Country Link
JP (1) JPS5923109B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5262351A (en) * 1990-08-21 1993-11-16 Thomson-Csf Process for manufacturing a multilayer integrated circuit interconnection
US5700715A (en) * 1994-06-14 1997-12-23 Lsi Logic Corporation Process for mounting a semiconductor device to a circuit substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5262351A (en) * 1990-08-21 1993-11-16 Thomson-Csf Process for manufacturing a multilayer integrated circuit interconnection
US5700715A (en) * 1994-06-14 1997-12-23 Lsi Logic Corporation Process for mounting a semiconductor device to a circuit substrate

Also Published As

Publication number Publication date
JPS5923109B2 (en) 1984-05-30

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