KR930006850B1 - 반도체장치의 제조방법 - Google Patents
반도체장치의 제조방법 Download PDFInfo
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- KR930006850B1 KR930006850B1 KR1019890019300A KR890019300A KR930006850B1 KR 930006850 B1 KR930006850 B1 KR 930006850B1 KR 1019890019300 A KR1019890019300 A KR 1019890019300A KR 890019300 A KR890019300 A KR 890019300A KR 930006850 B1 KR930006850 B1 KR 930006850B1
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Abstract
내용 없음.
Description
제1도는 이 발명의 한 실시예에 의한 반도체장치를 표시하는 단면도.
제2도 및 제3도는 종래의 반도체장치를 표시하는 단면도.
제4도는 알미늄 합금계의 단상벌크(bulk)를 에폭시수지로 봉하여 막은후, 고온보존한 실험샘플의 단면도.
제5도는 동·알미늄의 벌크를 압연한 후, 열처리하여 제조한 다상벌크를 에폭시 수지후, 고온보존한 실험샘플의 단면도.
제6도 및 제7도는 제3도의 반도체장치를 고온보존한 후의 동·알미늄 접합부의 단면도.
제8도~제10도는 제1도~제3도의 동불(ball)의 접합면의 상태를 표시하는 모식도(模式圖).
제11도는 고온신뢰성 시험에 있어서 종래의 반도체장치와 이 발명의 반도체장치의 보존시간과 불량 발생율을 표시하는 와이블 플롯(weibull plot)을 표시하는 도면.
* 도면의 주요부분에 대한 부호의 설명
11: Si기판 12 : SiO2막
13 : Al막 15 : 실리콘수지
14 : 리드플레임의 다이패드 21 : 동와이어
21 : 압착부의 동볼 31 : θ상(CuAl2)
또한, 각 도중의 동일부호는 동일 또는 상당부분을 표시한다.
이 발명은, 반도체소자의 전극과 외부리드와의 배선에 금속의 가는선을 사용하여 금와이어 이상의 높은 신뢰성을 확보할 수 있도록 한 반도체장치의 제조방법에 관한 것이다.
제2도, 제3도는 종래의 반도체장치를 표시하는 단면도이며, 이들의 도면에 있어서 11은 Si기판, 12는 SiO2막, 13은 Al막이다.
이들은 반도체소자의 전극부 구조이며, 14는 상기Si기판(11)이 접합되는 리드플레임의 다이패드로서, 접합재는 에폭시수지(16) 또는 Au-Si납땜 (17)이 사용되고 있다.
21은 금속의 가는선(동와이어)으로, 이 동화이어(21)는, 앞끝단을 가열하는 것으로서 용해시키고 동볼(22)을 생성하여, 이것을 캐필러리팁(capillary tip)(도시하지 않음)에서 Al막(13)에 꽉눌러, 소성(塑性)변형시킴과 아울러, 초음파 에너지와 Si기판(11)에 가하여지는 열에너지(250℃~400℃)에 의하여 Al막(13)과 압착후의 동볼(22)과의 사이에 금속간화합물(31~33)의 합금층을 생성시킨다.
이 금속간 화합물(31~33)중, 31은 θ(CuAl2), 32는 η2상(CuAl), 33은 γ2상(Cu9Al4)이다. 반도체장치로서는 이후, 속이 빈 세라믹에 봉하여 막히던가, 에폭시 수지로 봉하여 막게 된다.
이 단면의 관찰결과에서, 제2도의 θ상(31)은 두께의 분산이 크고, 불균일한 합금층이며 제3도의 θ상(31), η2상(32), γ2상(33)은 두께의 분산은 적고 균일한 합금층이 생성되어 있는 것으로 판정된다.
또, 합금층의 평가방법으로서, 접합부의 Al막(13)을 인산(A3PO4)으로 에치후, 압착한 동볼(22)을 수산화나트륨(NaOH)의 수용액으로 색깔을 나타내고, 접합면이 갈색이 되는 것으로서 θ상(31)의 생성을 관찰하여, 합금층의 상의 동정(同定)이 된다. 이 제9도는, 제2도의 접합면의 상태를 표시하는 도면으로, 갈색으로 색갈이 나타나는 부분(θ상)(31)이 면전체에 없어 불균일하며, 갈색으로 색깔이 나타나지 않는 부분, 즉 합금층의 θ상(31)이 생성하지 않은 동의면이 많이 관찰된다.
제10도는 마찬가지로, 제3도의 접합면의 상태를 표시하는 도면으로, 갈색으로 색깔이 나타나는 부분(θ상)(31)이 면전체에 있는 것으로, 이 이외의 백색 또는 청색으로 색깔이 나타나는 부분도 산재하여, 합금층의 θ상(31)이 생성하고 있는 것으로 η2상(32) 또는 γ2상(33)도 부분적으로 생성하고 있는 것을 표시하고 있다.
또, 특개소 62-265729호 공보에 표시된 종래의 반도체장치는, 그 명세서의 내용에서 합금층이 θ상, η2상, γ2상의 3종류가 공존하는 제3도 및 제10도의 상태에 가까운 것이라 추정된다. 종래의 반도체장치의 접합부는, 이상과 같은 구성을 갖고, 이것을 에폭시 수지로서 봉하여 막던가, 또는 속이 빈 상태에서 세라믹재에 의하여 봉하여 막던가하고 있다.
일반적으로는 이것을 가속의 신뢰성 시험을 행하여 반도체장치의 품질평가로 한다. 세라믹으로 봉하여 막는 경우에는 특히 문제는 없으나, 에폭시 수지로 봉하여 막는 경우, 같은 배선을 금와이어로서 행하였을때에 대하여, 품질의 불균형이 크고, 또 고온에서의 수명도 금와이어의 경우와 마찬가지며, 동와이어를 사용하는 메리트의 하나인 고온영역에의 동작마진을 넓힐수가 없다는 문제점이 있었다.
이 발명은, 상기와 같은 문제점을 해결하기 위하여 이루어진 것으로서, 고온하의 에폭시 수지의 봉하여 막는 내부에서 생기는 동·알미늄 합금층의 열화(劣化)를 억제하고, 품질의 균일한 반도체장치의 제조방법을 얻는것을 목적으로 한다.
이 발명에 관한 반도체장치는, 반도체소자와 리드 플레임의 다이패드를 접합하는 접합재로서 실리콘 수지를 사용함과 아울러, 상기 전극과 금속의 가는선과의 접합부의 금속간 화합물의 주된 조성이 CuAL2가 되도록 상기 알미늄과 금속의 가는선과의 본딩(bonding)을 행하는 것이다. 이 발명에 있어서는, 금속의 가는선의 Al막과의 접합부에 균일한 θ상이 형성되어, 에폭시 수지에 의한 봉하여 막은 후의 고온보존에 있어서도 열화의 진행이 방지된다.
[실시예]
이하, 이 발명에 관하여 설명하지만 우선 그 경위에 관하여 설명한다.
동·알미늄 합금계의 에폭시 수지에 봉하여 막힌 상태에서의 거동을 조사하기 위하여, 단상벌크의 η2상(CuAl), η2상(Cu9Al4), θ(CuAl2) 각 1조와 벌크 Al과 벌크 Cu를 표면 세정화후, 압연열확산시켜 제작한 벌크를 준비하여 이들을 에폭시수지 중에 봉하여 막은 후, 고온보존하여 단면을 관찰하였다.
제4도(a)~(c)는 단상벌크, 제5도는 다상벌크의 단면관찰 결과를 모식적으로 표시한 것이다.
제4도의 단상벌크에서는, η2상(32)[제4도(b)]과 η2상(33)[제4도(a)]는 벌크의 주위에 열화한 η2상((34)과 γ2상(35)이 관찰되었으나, θ상(31)이 열화는 관찰되지 않앗다.
또, 다상벌크에 관하여도 제5도에 표시하는 것과 같이 벌크 Al(18), 벌크 Cu(23), θ상(31)은 열화하지 않고, η2상(34)와 γ2상(35)은 열화하였다.
이들의 해석결과에서 동·알미늄 합금계 중에는, 에폭시 수지로 봉하여 막은후, 고온보존을 행한 경우, 선택적으로 열화가 진행하는 합금상이 존재하는 것이 판명되었다.
또, 이들의 것을 실제의 Al전극과 동와이어의 본딩의 경우에 관하여 관찰하였다. 즉, 제3도에 표시한 반도체장치를 250℃의 항온욕조중에 고온보존하고, 전극과 동와이어(21)의 도통저항을 측정하는 것으로서, 접합부의 열화를 판정하여, 이 관찰결과를 제6도에 도시된 바와같이 20시간 후의 접합부의 단면도로 하고, 제7도에 도시된 바와같이 30시간후의 접합부의 단면도로서 표시한다.
제6도는 열화가 동볼(22)과 Al막(13)면의 경계에서 동볼(22)의 내부를 향하여 진행함과 아울러, 크게 퍼져서 동볼(22)의 주변의 Al막(13)측에는 θ상(31)이 또, 열화가 진해하고 있지않는 동볼(22)의 내부에는, η2상(34)와 γ2상(35)가 관찰된다. 도, 제7도는 접합부의 전부가 완전히 열화하고 있는 상태가 관찰된다.
이들은 250℃의 고오보존에서는, 열화와 동·알미늄 합금층의 성장이 동시에 진행하기 위하여 벌크에서 판명한 η2상(34)와 γ2상(35)의 성장과 더불어 열화하는 η2상(34)과 γ2상(35)도 동시에 퍼진것이라 판단할 수가 있다.
또한, 반도체장치로서의 수명은 제6도와 제7도의 도중에 존재한다.
이상의 실험결과를 기초로하여, 동화이어(21)를 상요한 반도체장치의 고온보존의 신뢰성을 향상시키기 위하여는, 균일한 θ상(31)만을 접합부에 생성하는 것이다라고 결론지었다.
이하, 이 발명의 한 실시예를 제1도에 관하여 설명한다.
제1도에 있어서는, 14는 다이패드이며 동합금 플레임의 일부로서, 이것과 반도체장치의 Si기판(11)은 실리콘수지(15)에 의하여 접합되어 있어 여기에 있어서, 종래와 마찬가지로 와이어 본드법에 의하여 Al막(13)에 압착후의 동볼(22)와의 접합부에, θ상(31)만의 합금층을 생성할 수가 있다.
이것은, Al원자 중에 Cu원자가 2:1의 비율로 확산될때에 θ상(CuAl2)(31)이 생성되고, Cu원자와 Al원자를 통상, 일정한 온도하에서 가압하는 경우에 비하여, Cu원자가 Al원자중에 확산하는 속도가 크게될때 즉, Cu원자가 Al원자의 온도보다도 높을것 또는 Al원자의 진동이 Cu원자의 진동보다도 클것이 θ상(31)을 통상이상으로 생성시키는 것이 된다고 생각된다.
반도체장치로서는 이후, 속이빈 세라믹으로 봉하여 막던가, 에폭시 수지로 봉하여 막게 된다. θ상(31)만의 합금층이 생성된 반도체장치를 250℃ 고온보존하면, 초기에 있어서 생성하고 있지 않는 η2상(32)와 γ2상(33)이 순차 생성함과 아울러, 주위의 에폭시수지의 영향에 의하여, 열화가 시작되어 , 열화와 합금층의 성장이 동시에 신행하는 결과, 제6도에 표시한 상태에서 수명이 다한다.
또, θ상(31)의 평가방법으로서, 반제품을 임의로 뽑아내어, 종래의 기술에서 기술한 인산에 의한 에칭과 수산화나트륨 수용액에 의한 색깔이 나타나서, 접합면 전체의 80% 이상이 갈색으로 색깔이 나타나 있는 것을 확인하고, 안정된 품질을 유지하면서 제조를 행할 수가 있다.
제8도에 θ상(31)이, 접합면 전체에 균일하게 생성한 상태의 모식도를 표시한다. 이 발명의 특징적인 점은, 반도체소자와 다이패드의 접합을 행하는 다이본드재를 최적화한 것이며, 제1표에 종래의 에폭시수지와 Au-Ai땜납, 이번회의 실리콘 수지의 특성비교를 표시한다.
이중 Au-Si 땜납은 와이어 본드시의 가열온도 이상의 고온의 사용에 견디며, 탄성율이 높고 η2상, γ2상, θ상의 모든 합금계를 생성하기 쉽다.
이것에 대하여, 에폭시 수지는 유리 전이점(Tg)이 와이어 본드시의 가열온도 이하에서 Al막과 동본의 접합시에, 수지가 열화하여 탄성율의 저하가 일어나 불균일한 θ상 밖에 생성할 수 없다.
그러나, 실리콘 수지는 유리 전이점(Tg)가 와이어 본드시의 가열온도의 훨씬 아래인 영하이지만, 수지의 열화가 일어나지 않고, 탄성율이 안정되어 있으므로, 균일적인 θ상을 생성할 수가 있다.
따라서, 상기에서는 실리콘 수지를 사용하였으나 실온에서 400℃까지의 탄성율이 1.0×102kg/cm2이하의 것이면, 다른재료에서도 같은 효과가 얻어진다. 최후로, 제11도는 250℃ 고온보존시의 반도체장치의 신뢰성 수명의 비교를 표시하는 그래프로서, 5가 이번회의 발명, 6은 종래의 것을 표시한다. 종래 20-30 시간의 수명이 금회의 발명에 의하여 100-130시간까지 수명을 연장할 수가 있었다.
이상 설명한 것과 같이 이 발명은 리드플레임의 다이패드에 접합된 반도체소자의 전극의 주된 조성이 알미늄이며, 전극와 외부 리드와의 배선이 동합금의 금속의 가는선으로 본딩된 후, 수지로 봉하여 막은 반도체장치의 제조방법에 있어서, 반도체소자와 리드플레임의 다이패드를 접합하는 접합재로서 실리콘 수지를 사용함과 아울러, 전극과 금속의 가는선과의 접합부의 금속간 화합물의 주된 조성을 CuAl2로하여 상기 알미늄과 금속의 가는선과의 본딩을 행하도록 하였으므로, 고온 신뢰성이 향상된 반도체장치를 안정되게 제조할 수 있는 효과가 있다.
Claims (2)
- 리드플레임과 다이패드(14)사이에 배치되고 실온에서 약 400℃까지의 탄성율이 1kg/cm2와 100kg/cm2사이의 범위를 갖는 접합재(15)로 알미늄전극(13)을 갖는 반도체칩을 상기 리드플레임의 다이패드(14)에 접합하는 공정과, 동 와이어(21)이 끝단을 가열하여 동볼(22)을 형성하는 공정과, 상기 알미늄전극(13)을 가열하고 아울러 상기 동볼(22)을 상기 가열된 알미늄전극(13)상에 가압하면서 초음파 에너지를 상기 가열된 알미늄전극(13)에 제공하여, 상기 동볼(22)을 소성적으로 변형하고 아울러 상기 변형된 동볼(22)이 상기 알미늄전극(13)에 접촉되는 영역에서 동과 알미늄의 θ상 금속간 화합물(CuAl2)을 형성하는 공정과, 상기 알미늄전극(13)과 상기 동와이어(21)사이의 접합을 에폭시수지로 봉지하는 공정을 포함하는 반도체장치의 제조방법.
- 제1항에 있어서, 상기 접합재(15)는 실리콘수지로서 상기 반도체칩을 접합하는 반도체장치의 제조방법.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP89-6827 | 1989-01-13 | ||
JP1006827A JPH0817189B2 (ja) | 1989-01-13 | 1989-01-13 | 半導体装置の製造方法 |
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Publication Number | Publication Date |
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KR900012342A KR900012342A (ko) | 1990-08-03 |
KR930006850B1 true KR930006850B1 (ko) | 1993-07-24 |
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KR1019890019300A KR930006850B1 (ko) | 1989-01-13 | 1989-12-22 | 반도체장치의 제조방법 |
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Country | Link |
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US (1) | US5116783A (ko) |
JP (1) | JPH0817189B2 (ko) |
KR (1) | KR930006850B1 (ko) |
DE (1) | DE3938152C2 (ko) |
Families Citing this family (17)
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US5229646A (en) * | 1989-01-13 | 1993-07-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with a copper wires ball bonded to aluminum electrodes |
JPH03208355A (ja) * | 1990-01-10 | 1991-09-11 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
JP2843658B2 (ja) * | 1990-08-02 | 1999-01-06 | 東レ・ダウコーニング・シリコーン株式会社 | フリップチップ型半導体装置 |
US5681779A (en) * | 1994-02-04 | 1997-10-28 | Lsi Logic Corporation | Method of doping metal layers for electromigration resistance |
US5771157A (en) * | 1996-03-08 | 1998-06-23 | Honeywell, Inc. | Chip-on-board printed circuit assembly using aluminum wire bonded to copper pads |
JP3504448B2 (ja) * | 1996-10-17 | 2004-03-08 | 株式会社ルネサステクノロジ | 半導体装置 |
US6464324B1 (en) * | 2000-01-31 | 2002-10-15 | Picojet, Inc. | Microfluid device and ultrasonic bonding process |
US20060050109A1 (en) * | 2000-01-31 | 2006-03-09 | Le Hue P | Low bonding temperature and pressure ultrasonic bonding process for making a microfluid device |
US7081240B1 (en) * | 2000-06-28 | 2006-07-25 | Zimmer Orthobiologics, Inc. | Protein mixtures for wound healing |
TWI221026B (en) * | 2002-12-06 | 2004-09-11 | Nat Univ Chung Cheng | Method of thermosonic wire bonding process for copper connection in a chip |
US7791198B2 (en) | 2007-02-20 | 2010-09-07 | Nec Electronics Corporation | Semiconductor device including a coupling region which includes layers of aluminum and copper alloys |
JP5550369B2 (ja) * | 2010-02-03 | 2014-07-16 | 新日鉄住金マテリアルズ株式会社 | 半導体用銅ボンディングワイヤとその接合構造 |
JP2016028417A (ja) * | 2014-07-11 | 2016-02-25 | ローム株式会社 | 電子装置 |
JP6810222B2 (ja) * | 2014-07-11 | 2021-01-06 | ローム株式会社 | 電子装置 |
JP6607771B2 (ja) * | 2015-12-03 | 2019-11-20 | ローム株式会社 | 半導体装置 |
US9576929B1 (en) * | 2015-12-30 | 2017-02-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-strike process for bonding |
JP2020072169A (ja) * | 2018-10-31 | 2020-05-07 | ルネサスエレクトロニクス株式会社 | 半導体装置及び半導体装置の製造方法 |
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US3125803A (en) * | 1960-10-24 | 1964-03-24 | Terminals | |
NL286149A (ko) * | 1961-12-04 | 1900-01-01 | ||
US3790866A (en) * | 1973-05-14 | 1974-02-05 | Gen Motors Corp | Semiconductor device enclosure and method of making same |
US4139726A (en) * | 1978-01-16 | 1979-02-13 | Allen-Bradley Company | Packaged microcircuit and method for assembly thereof |
JPS55105339A (en) * | 1979-02-07 | 1980-08-12 | Toshiba Corp | Ultrasonic bonding method |
JPS60194534A (ja) * | 1984-03-16 | 1985-10-03 | Toshiba Corp | ボンデイング装置 |
JPS6189643A (ja) * | 1984-10-09 | 1986-05-07 | Toshiba Corp | 半導体装置及びその製造方法 |
JPS61287155A (ja) * | 1985-06-14 | 1986-12-17 | Hitachi Ltd | 半導体装置及び半導体装置の製造方法 |
DE3641524A1 (de) * | 1985-12-10 | 1987-06-11 | Mitsubishi Electric Corp | Verfahren zur herstellung eines halbleiterbauelements |
JPS62265729A (ja) * | 1986-05-14 | 1987-11-18 | Hitachi Ltd | 半導体装置 |
JPS63164329A (ja) * | 1986-12-26 | 1988-07-07 | Toshiba Corp | 半導体装置 |
JPS63250828A (ja) * | 1987-04-08 | 1988-10-18 | Hitachi Ltd | 半導体装置 |
JPH0748507B2 (ja) * | 1987-08-18 | 1995-05-24 | 三菱電機株式会社 | ワイヤボンデイング方法 |
JPH0734449B2 (ja) * | 1987-11-30 | 1995-04-12 | 三菱電機株式会社 | 半導体装置の電極接合部構造 |
JPH01201933A (ja) * | 1988-02-08 | 1989-08-14 | Mitsubishi Electric Corp | ワイヤボンディング方法及びその装置 |
JPH01201934A (ja) * | 1988-02-08 | 1989-08-14 | Mitsubishi Electric Corp | ワイヤボンディング方法及びキャピラリチップ |
US4842662A (en) * | 1988-06-01 | 1989-06-27 | Hewlett-Packard Company | Process for bonding integrated circuit components |
-
1989
- 1989-01-13 JP JP1006827A patent/JPH0817189B2/ja not_active Expired - Lifetime
- 1989-08-11 US US07/392,553 patent/US5116783A/en not_active Expired - Lifetime
- 1989-11-16 DE DE3938152A patent/DE3938152C2/de not_active Expired - Fee Related
- 1989-12-22 KR KR1019890019300A patent/KR930006850B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
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DE3938152C2 (de) | 1994-05-05 |
KR900012342A (ko) | 1990-08-03 |
JPH02187042A (ja) | 1990-07-23 |
DE3938152A1 (de) | 1990-07-26 |
JPH0817189B2 (ja) | 1996-02-21 |
US5116783A (en) | 1992-05-26 |
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