KR930005352A - 반도체 집적회로 - Google Patents

반도체 집적회로 Download PDF

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Publication number
KR930005352A
KR930005352A KR1019920014150A KR920014150A KR930005352A KR 930005352 A KR930005352 A KR 930005352A KR 1019920014150 A KR1019920014150 A KR 1019920014150A KR 920014150 A KR920014150 A KR 920014150A KR 930005352 A KR930005352 A KR 930005352A
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KR
South Korea
Prior art keywords
clock signal
divider
output
ring oscillator
frequency
Prior art date
Application number
KR1019920014150A
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English (en)
Other versions
KR100192832B1 (ko
Inventor
지아끼 다까노
Original Assignee
오가 노리오
소니 가부시기가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 오가 노리오, 소니 가부시기가이샤 filed Critical 오가 노리오
Publication of KR930005352A publication Critical patent/KR930005352A/ko
Application granted granted Critical
Publication of KR100192832B1 publication Critical patent/KR100192832B1/ko

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H03L7/0997—Controlling the number of delay elements connected in series in the ring oscillator
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Dram (AREA)

Abstract

내용 없음.

Description

반도체 집적회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본원발명의 도시한 반도체집적회로의 구성도,
제2도는 위상비교기의 일예를 도시한 구성도,
제3도는 위상진행시의 동작을 도시한 타임차트,
제4도는 위상지연시의 동작을 도시한 타임차트,
제5도는 저속동작직접회로와 고속동작직접회로가 혼재되어 있는 회로를 동작시키는 일예를 도시한 구성도.

Claims (3)

  1. 회로를 구성하는 각 소자의 지연시간의 합계에 의해 정해지는 발진주파수가 가변의 링오실레이터와, 상기 링오실레이터로부터 부여되는 발진출력을 소정수로 분주(分周)하여 출력하는 분주기와, 상기 분주기로부터 부여되는 분주기출력신호와 외부로부터 부여되는 외부클록신호의 주파수와를 비교하는 위상비교기와, 상기 위상비교기로부터 출력되는 비교출력에 따라서 상기 링오실레이터의 발진주파수를 제어하는 업다운카운터로 이루어지는 클록신호발생신호를 구비하는 것을 특징으로 하는 반도체집적회로
  2. 회로를 구성하는 각 소자의 지연시간의 합계에 의해 정해지는 발진주파수가 가변의 링오실레이터와, 상기 링오실레이터로부터 부여되는 발진출력을 소정수로 분주하여 출력하는 분주기와, 상기 분주기로부터 부여되는 분주기출력신호와 외부로부터 부여되는 외부클록신호의 주파수와를 비교하는 위상비교기와, 상기 위상비교기로부터 출력되는 비교출력 따라서 상기링오실레이터의 발진주파수를 제어하는 업다운카운터로 이루어지는 클록신호발생회로를 구비하고, 외부로부터 클록신호가 부여되었을 때에, 상기 외부입력클록신호에 제어되는 동시에, 상기 외부입력클록신호보다 주파수가 높은 내부클록신호를 발생시켜서, 상기 외부클록신호 및 내부클록신호의 양쪽을 외부에 출력할 수 있도록 한 것을 특징으로 하는 반도체집적회로.
  3. 화합물반도체에 의해 구성되는 동시에, 회로를 구성하는 각 소자의 지연시간의 합계에 의해 정해지는 발진주파수가 가변의 링오실레이터와, 상기 링오실레이터로부터 부여되는 발진출력을 소정수로 분주하여 출력하는 분주기와, 상기 분주기로부터 부여되는 분주기출력신호와 외부로부터 부여되는 외부클록신호의 주파수와를 비교하는 위상비교기와, 상기 위상비교기로부터 출력되는 비교출력에 따라서 상기 링오실레이터의 발진주파수를 제어하는 업다운카운터로 이루어지는 클록신호발생회로를 구비하고, 외부로부터 부여되는 클록신호보다 높은 주파수의 내부클록신호를 발생시켜서, 상기 내부발생의 클록신호를 가지고 내부회로를 고속으로 동작시키도록 한 것을 특징으로 하는 반도체집적회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920014150A 1991-08-09 1992-08-07 반도체집적회로 KR100192832B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP91-224,766 1991-08-09
JP3224766A JPH0548446A (ja) 1991-08-09 1991-08-09 半導体集積回路

Publications (2)

Publication Number Publication Date
KR930005352A true KR930005352A (ko) 1993-03-23
KR100192832B1 KR100192832B1 (ko) 1999-06-15

Family

ID=16818893

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920014150A KR100192832B1 (ko) 1991-08-09 1992-08-07 반도체집적회로

Country Status (5)

Country Link
US (1) US5329254A (ko)
EP (1) EP0528283B1 (ko)
JP (1) JPH0548446A (ko)
KR (1) KR100192832B1 (ko)
DE (1) DE69229087T2 (ko)

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Also Published As

Publication number Publication date
EP0528283B1 (en) 1999-05-06
EP0528283A2 (en) 1993-02-24
US5329254A (en) 1994-07-12
DE69229087T2 (de) 1999-11-11
EP0528283A3 (en) 1993-07-07
DE69229087D1 (de) 1999-06-10
KR100192832B1 (ko) 1999-06-15
JPH0548446A (ja) 1993-02-26

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