KR920022553A - Ldd 소자의 구조 및 제조방법 - Google Patents

Ldd 소자의 구조 및 제조방법 Download PDF

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Publication number
KR920022553A
KR920022553A KR1019910007882A KR910007882A KR920022553A KR 920022553 A KR920022553 A KR 920022553A KR 1019910007882 A KR1019910007882 A KR 1019910007882A KR 910007882 A KR910007882 A KR 910007882A KR 920022553 A KR920022553 A KR 920022553A
Authority
KR
South Korea
Prior art keywords
forming
gate
ion implantation
nitride film
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1019910007882A
Other languages
English (en)
Korean (ko)
Inventor
신형순
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019910007882A priority Critical patent/KR920022553A/ko
Priority to DE4208537A priority patent/DE4208537C2/de
Priority to JP4123685A priority patent/JPH06204469A/ja
Publication of KR920022553A publication Critical patent/KR920022553A/ko
Priority to TW082107852A priority patent/TW252210B/zh
Priority to US08/873,949 priority patent/US5904530A/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0225—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate using an initial gate mask complementary to the prospective gate location, e.g. using dummy source and drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/299—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations
    • H10D62/307—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations the doping variations being parallel to the channel lengths
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/018—Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0147—Manufacturing their gate sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0217—Manufacture or treatment of FETs having insulated gates [IGFET] forming self-aligned punch-through stoppers or threshold implants under gate regions

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
KR1019910007882A 1991-05-15 1991-05-15 Ldd 소자의 구조 및 제조방법 Ceased KR920022553A (ko)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1019910007882A KR920022553A (ko) 1991-05-15 1991-05-15 Ldd 소자의 구조 및 제조방법
DE4208537A DE4208537C2 (de) 1991-05-15 1992-03-17 MOS-FET-Struktur und Verfahren zu deren Herstellung
JP4123685A JPH06204469A (ja) 1991-05-15 1992-05-15 電界効果トランジスタおよびその製造方法
TW082107852A TW252210B (enExample) 1991-05-15 1993-09-23
US08/873,949 US5904530A (en) 1991-05-15 1997-06-12 Method of making LDD structure spaced from channel doped region

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910007882A KR920022553A (ko) 1991-05-15 1991-05-15 Ldd 소자의 구조 및 제조방법

Publications (1)

Publication Number Publication Date
KR920022553A true KR920022553A (ko) 1992-12-19

Family

ID=19314488

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910007882A Ceased KR920022553A (ko) 1991-05-15 1991-05-15 Ldd 소자의 구조 및 제조방법

Country Status (5)

Country Link
US (1) US5904530A (enExample)
JP (1) JPH06204469A (enExample)
KR (1) KR920022553A (enExample)
DE (1) DE4208537C2 (enExample)
TW (1) TW252210B (enExample)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3125726B2 (ja) * 1997-08-26 2001-01-22 日本電気株式会社 半導体装置の製造方法
JP2000049344A (ja) * 1998-07-31 2000-02-18 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6180468B1 (en) * 1998-10-23 2001-01-30 Advanced Micro Devices Inc. Very low thermal budget channel implant process for semiconductors
US6225173B1 (en) * 1998-11-06 2001-05-01 Advanced Micro Devices, Inc. Recessed channel structure for manufacturing shallow source/drain extensions
US6200869B1 (en) 1998-11-06 2001-03-13 Advanced Micro Devices, Inc. Method of fabricating an integrated circuit with ultra-shallow source/drain extensions
FR2788629B1 (fr) * 1999-01-15 2003-06-20 Commissariat Energie Atomique Transistor mis et procede de fabrication d'un tel transistor sur un substrat semiconducteur
JP2000332236A (ja) * 1999-05-18 2000-11-30 Univ Hiroshima 微細化に適した新しい高性能ｍｏｓｆｅｔ
US6355528B1 (en) * 1999-08-11 2002-03-12 Advanced Micro Devices, Inc. Method to form narrow structure using double-damascene process
DE19957540B4 (de) 1999-11-30 2005-07-07 Infineon Technologies Ag Verfahren zum Herstellen eines Feldeffekttransistors mit Anti-Punch-Through-Implantationsgebiet
US6541829B2 (en) * 1999-12-03 2003-04-01 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US6333244B1 (en) 2000-01-26 2001-12-25 Advanced Micro Devices, Inc. CMOS fabrication process with differential rapid thermal anneal scheme
US6420218B1 (en) 2000-04-24 2002-07-16 Advanced Micro Devices, Inc. Ultra-thin-body SOI MOS transistors having recessed source and drain regions
US6368947B1 (en) 2000-06-20 2002-04-09 Advanced Micro Devices, Inc. Process utilizing a cap layer optimized to reduce gate line over-melt
US6361874B1 (en) 2000-06-20 2002-03-26 Advanced Micro Devices, Inc. Dual amorphization process optimized to reduce gate line over-melt
US6630386B1 (en) 2000-07-18 2003-10-07 Advanced Micro Devices, Inc CMOS manufacturing process with self-amorphized source/drain junctions and extensions
US6521502B1 (en) 2000-08-07 2003-02-18 Advanced Micro Devices, Inc. Solid phase epitaxy activation process for source/drain junction extensions and halo regions
KR100378183B1 (ko) 2000-09-18 2003-03-29 삼성전자주식회사 반도체 메모리 장치 및 그의 제조 방법
US6853029B2 (en) * 2001-05-28 2005-02-08 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device with multi-layer gate structure
US6756619B2 (en) * 2002-08-26 2004-06-29 Micron Technology, Inc. Semiconductor constructions
JP2007088488A (ja) * 2006-10-18 2007-04-05 Renesas Technology Corp 電界効果トランジスタ及びその製造方法
US9117687B2 (en) * 2011-10-28 2015-08-25 Texas Instruments Incorporated High voltage CMOS with triple gate oxide
US9117691B2 (en) * 2012-12-28 2015-08-25 Texas Instruments Incorporated Low cost transistors
CN105633156A (zh) * 2015-02-09 2016-06-01 中国科学院微电子研究所 半导体器件及其制造方法
CN111092120B (zh) * 2018-10-24 2024-05-14 长鑫存储技术有限公司 场效应管器件的制造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61256769A (ja) * 1985-05-10 1986-11-14 Toshiba Corp 半導体装置
JPS63129664A (ja) * 1986-11-20 1988-06-02 Toshiba Corp 半導体装置の製造方法
JPS63241965A (ja) * 1987-03-30 1988-10-07 Toshiba Corp 絶縁ゲ−ト型電界効果トランジスタおよびその製造方法
FR2625044B1 (fr) * 1987-12-18 1990-08-31 Commissariat Energie Atomique Transistor mos a extremite d'interface dielectrique de grille/substrat relevee et procede de fabrication de ce transistor
JPH0290567A (ja) * 1988-09-28 1990-03-30 Hitachi Ltd 半導体装置とその製造方法
JPH02174168A (ja) * 1988-12-26 1990-07-05 Nippon Telegr & Teleph Corp <Ntt> Ｍｉｓ電界型トランジスタ
US5082794A (en) * 1989-02-13 1992-01-21 Motorola, Inc. Method of fabricating mos transistors using selective polysilicon deposition
US5073512A (en) * 1989-04-21 1991-12-17 Nec Corporation Method of manufacturing insulated gate field effect transistor having a high impurity density region beneath the channel region
JPH036863A (ja) * 1989-06-05 1991-01-14 Takehide Shirato 半導体装置

Also Published As

Publication number Publication date
DE4208537A1 (de) 1992-11-19
TW252210B (enExample) 1995-07-21
DE4208537C2 (de) 1997-04-17
US5904530A (en) 1999-05-18
JPH06204469A (ja) 1994-07-22

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