TW252210B - - Google Patents
Info
- Publication number
- TW252210B TW252210B TW082107852A TW82107852A TW252210B TW 252210 B TW252210 B TW 252210B TW 082107852 A TW082107852 A TW 082107852A TW 82107852 A TW82107852 A TW 82107852A TW 252210 B TW252210 B TW 252210B
- Authority
- TW
- Taiwan
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/66583—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910007882A KR920022553A (ko) | 1991-05-15 | 1991-05-15 | Ldd 소자의 구조 및 제조방법 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW252210B true TW252210B (zh) | 1995-07-21 |
Family
ID=19314488
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW082107852A TW252210B (zh) | 1991-05-15 | 1993-09-23 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5904530A (zh) |
JP (1) | JPH06204469A (zh) |
KR (1) | KR920022553A (zh) |
DE (1) | DE4208537C2 (zh) |
TW (1) | TW252210B (zh) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3125726B2 (ja) * | 1997-08-26 | 2001-01-22 | 日本電気株式会社 | 半導体装置の製造方法 |
JP2000049344A (ja) * | 1998-07-31 | 2000-02-18 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US6180468B1 (en) * | 1998-10-23 | 2001-01-30 | Advanced Micro Devices Inc. | Very low thermal budget channel implant process for semiconductors |
US6225173B1 (en) * | 1998-11-06 | 2001-05-01 | Advanced Micro Devices, Inc. | Recessed channel structure for manufacturing shallow source/drain extensions |
US6200869B1 (en) | 1998-11-06 | 2001-03-13 | Advanced Micro Devices, Inc. | Method of fabricating an integrated circuit with ultra-shallow source/drain extensions |
FR2788629B1 (fr) * | 1999-01-15 | 2003-06-20 | Commissariat Energie Atomique | Transistor mis et procede de fabrication d'un tel transistor sur un substrat semiconducteur |
JP2000332236A (ja) * | 1999-05-18 | 2000-11-30 | Univ Hiroshima | 微細化に適した新しい高性能mosfet |
US6355528B1 (en) * | 1999-08-11 | 2002-03-12 | Advanced Micro Devices, Inc. | Method to form narrow structure using double-damascene process |
DE19957540B4 (de) | 1999-11-30 | 2005-07-07 | Infineon Technologies Ag | Verfahren zum Herstellen eines Feldeffekttransistors mit Anti-Punch-Through-Implantationsgebiet |
US6541829B2 (en) * | 1999-12-03 | 2003-04-01 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US6333244B1 (en) | 2000-01-26 | 2001-12-25 | Advanced Micro Devices, Inc. | CMOS fabrication process with differential rapid thermal anneal scheme |
US6420218B1 (en) | 2000-04-24 | 2002-07-16 | Advanced Micro Devices, Inc. | Ultra-thin-body SOI MOS transistors having recessed source and drain regions |
US6368947B1 (en) | 2000-06-20 | 2002-04-09 | Advanced Micro Devices, Inc. | Process utilizing a cap layer optimized to reduce gate line over-melt |
US6361874B1 (en) | 2000-06-20 | 2002-03-26 | Advanced Micro Devices, Inc. | Dual amorphization process optimized to reduce gate line over-melt |
US6630386B1 (en) | 2000-07-18 | 2003-10-07 | Advanced Micro Devices, Inc | CMOS manufacturing process with self-amorphized source/drain junctions and extensions |
US6521502B1 (en) | 2000-08-07 | 2003-02-18 | Advanced Micro Devices, Inc. | Solid phase epitaxy activation process for source/drain junction extensions and halo regions |
KR100378183B1 (ko) | 2000-09-18 | 2003-03-29 | 삼성전자주식회사 | 반도체 메모리 장치 및 그의 제조 방법 |
KR100436673B1 (ko) * | 2001-05-28 | 2004-07-02 | 가부시끼가이샤 도시바 | 반도체 장치 및 그 제조 방법 |
US6756619B2 (en) * | 2002-08-26 | 2004-06-29 | Micron Technology, Inc. | Semiconductor constructions |
JP2007088488A (ja) * | 2006-10-18 | 2007-04-05 | Renesas Technology Corp | 電界効果トランジスタ及びその製造方法 |
US9117687B2 (en) * | 2011-10-28 | 2015-08-25 | Texas Instruments Incorporated | High voltage CMOS with triple gate oxide |
US9117691B2 (en) * | 2012-12-28 | 2015-08-25 | Texas Instruments Incorporated | Low cost transistors |
CN105633156A (zh) * | 2015-02-09 | 2016-06-01 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
CN111092120B (zh) * | 2018-10-24 | 2024-05-14 | 长鑫存储技术有限公司 | 场效应管器件的制造方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61256769A (ja) * | 1985-05-10 | 1986-11-14 | Toshiba Corp | 半導体装置 |
JPS63129664A (ja) * | 1986-11-20 | 1988-06-02 | Toshiba Corp | 半導体装置の製造方法 |
JPS63241965A (ja) * | 1987-03-30 | 1988-10-07 | Toshiba Corp | 絶縁ゲ−ト型電界効果トランジスタおよびその製造方法 |
FR2625044B1 (fr) * | 1987-12-18 | 1990-08-31 | Commissariat Energie Atomique | Transistor mos a extremite d'interface dielectrique de grille/substrat relevee et procede de fabrication de ce transistor |
JPH0290567A (ja) * | 1988-09-28 | 1990-03-30 | Hitachi Ltd | 半導体装置とその製造方法 |
JPH02174168A (ja) * | 1988-12-26 | 1990-07-05 | Nippon Telegr & Teleph Corp <Ntt> | Mis電界型トランジスタ |
US5082794A (en) * | 1989-02-13 | 1992-01-21 | Motorola, Inc. | Method of fabricating mos transistors using selective polysilicon deposition |
US5073512A (en) * | 1989-04-21 | 1991-12-17 | Nec Corporation | Method of manufacturing insulated gate field effect transistor having a high impurity density region beneath the channel region |
JPH036863A (ja) * | 1989-06-05 | 1991-01-14 | Takehide Shirato | 半導体装置 |
-
1991
- 1991-05-15 KR KR1019910007882A patent/KR920022553A/ko not_active Application Discontinuation
-
1992
- 1992-03-17 DE DE4208537A patent/DE4208537C2/de not_active Expired - Lifetime
- 1992-05-15 JP JP4123685A patent/JPH06204469A/ja active Pending
-
1993
- 1993-09-23 TW TW082107852A patent/TW252210B/zh not_active IP Right Cessation
-
1997
- 1997-06-12 US US08/873,949 patent/US5904530A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US5904530A (en) | 1999-05-18 |
JPH06204469A (ja) | 1994-07-22 |
DE4208537A1 (de) | 1992-11-19 |
DE4208537C2 (de) | 1997-04-17 |
KR920022553A (ko) | 1992-12-19 |
Similar Documents
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |