KR920017258A - 집적 회로 제조 방법 - Google Patents
집적 회로 제조 방법 Download PDFInfo
- Publication number
- KR920017258A KR920017258A KR1019920002542A KR920002542A KR920017258A KR 920017258 A KR920017258 A KR 920017258A KR 1019920002542 A KR1019920002542 A KR 1019920002542A KR 920002542 A KR920002542 A KR 920002542A KR 920017258 A KR920017258 A KR 920017258A
- Authority
- KR
- South Korea
- Prior art keywords
- amorphous silicon
- integrated circuit
- window
- depositing
- dielectric layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/055—Fuse
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 4도는 본 발명에 따른 몇몇 제조 단계에서 안티퓨즈 스택을 포함하는 집적 회로 일부의 단면도.
Claims (8)
- 기판(1)위에 복수의 패턴화된 전도체(3)를 형성시키는 단계에 의해 안티퓨즈를 형성시키는 단계와, 상기 패턴화된 전도체(3)위에 제1유전체층(7)을 침전시키는 단계와, 상기 패턴화된 전도체(3)의 상부 표면의 일부를 노출시키는 적어도 한 개의 제1윈도우를 형성하기 위해 상기 제1유전체 층을 패턴화시키는 단계, 상기 노출된 부분위에 무정형 실리콘(9)층을 형성시키는 단계를 포함하는 집적 회로 제조 방법.
- 제1항에 있어서, 상기 형성시키는 단계는 상기 노출부위를 덮기 위해 상기 무정형 실리콘(9)을 침전시키고 패턴화시키는 단계를 포함하는 집적 회로 제조 방법.
- 제2항에 있어서, 상기 무정형 실리콘(9)의 부분을 노출시키는 적어도 한 개의 제2윈도우를 형성하기 위해 제2유전체층(15)을 침전시키고 상기 제2유전체층(15)을 패턴하시키는 단계를 포함하는 집적 회로 제조 방법.
- 제3항에 있어서, 상기 적어도 한 개의 제2윈도우에 금속(17)을 침전시키는 단계를 포함하는 집적 회로 제조 방법.
- 제4항에 있어서, 상기 무정형 실리콘에 인접한 적어도 하나의 전도물질층을 침전시키는 단계를 포함하는 집적 회로 제조 방법.
- 제4항에 있어서, 상기 무정형 실리콘(9)과 상기 패턴화된 전도체(3) 혹은 상기 금속(17)사이에 있는 적어도 하나의 장벽물질층(5)을 침전시키는 단계를 포함하는 집적 회로 제조 방법.
- 제4항에 있어서, 상기 무정형 실리콘(9)을 프로그래밍하기 위해 무정형 실리콘(9)전면에 임계 전압을 초과한 전압을 인가하는 단계를 포함하는 집적 회로 제조 방법.
- 제1항에 있어서, 상기 제1윈도우는 0.5 : 1이하의 종횡비를 갖는 집적 회로 제조 방법.※참고사항:최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US661,736 | 1991-02-27 | ||
US07/661,736 US5100827A (en) | 1991-02-27 | 1991-02-27 | Buried antifuse |
Publications (2)
Publication Number | Publication Date |
---|---|
KR920017258A true KR920017258A (ko) | 1992-09-26 |
KR100234444B1 KR100234444B1 (ko) | 1999-12-15 |
Family
ID=24654892
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920002542A KR100234444B1 (ko) | 1991-02-27 | 1992-02-20 | 집적회로 제조방법 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5100827A (ko) |
EP (1) | EP0501687A3 (ko) |
JP (1) | JP2642559B2 (ko) |
KR (1) | KR100234444B1 (ko) |
TW (1) | TW234202B (ko) |
Families Citing this family (56)
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US5552627A (en) * | 1990-04-12 | 1996-09-03 | Actel Corporation | Electrically programmable antifuse incorporating dielectric and amorphous silicon interlayers |
US5404029A (en) * | 1990-04-12 | 1995-04-04 | Actel Corporation | Electrically programmable antifuse element |
US5381035A (en) * | 1992-09-23 | 1995-01-10 | Chen; Wenn-Jei | Metal-to-metal antifuse including etch stop layer |
US5541441A (en) * | 1994-10-06 | 1996-07-30 | Actel Corporation | Metal to metal antifuse |
US5543656A (en) * | 1990-04-12 | 1996-08-06 | Actel Corporation | Metal to metal antifuse |
US5272101A (en) * | 1990-04-12 | 1993-12-21 | Actel Corporation | Electrically programmable antifuse and fabrication processes |
US5614756A (en) * | 1990-04-12 | 1997-03-25 | Actel Corporation | Metal-to-metal antifuse with conductive |
US6171512B1 (en) | 1991-02-15 | 2001-01-09 | Canon Kabushiki Kaisha | Etching solution for etching porous silicon, etching method using the etching solution and method of preparing semiconductor member using the etching solution |
EP0509631A1 (en) * | 1991-04-18 | 1992-10-21 | Actel Corporation | Antifuses having minimum areas |
US5331197A (en) * | 1991-04-23 | 1994-07-19 | Canon Kabushiki Kaisha | Semiconductor memory device including gate electrode sandwiching a channel region |
US5557136A (en) * | 1991-04-26 | 1996-09-17 | Quicklogic Corporation | Programmable interconnect structures and programmable integrated circuits |
US5701027A (en) * | 1991-04-26 | 1997-12-23 | Quicklogic Corporation | Programmable interconnect structures and programmable integrated circuits |
US5196724A (en) * | 1991-04-26 | 1993-03-23 | Quicklogic Corporation | Programmable interconnect structures and programmable integrated circuits |
WO1993004499A1 (en) * | 1991-08-19 | 1993-03-04 | Crosspoint Solutions, Inc. | An improved antifuse and method of manufacture thereof |
EP0558176A1 (en) * | 1992-02-26 | 1993-09-01 | Actel Corporation | Metal-to-metal antifuse with improved diffusion barrier layer |
US5250464A (en) * | 1992-03-11 | 1993-10-05 | Texas Instruments Incorporated | Method of making a low capacitance, low resistance sidewall antifuse structure |
EP0564138A1 (en) * | 1992-03-31 | 1993-10-06 | STMicroelectronics, Inc. | Field programmable device |
EP0583119B1 (en) * | 1992-07-31 | 2000-02-09 | STMicroelectronics, Inc. | Programmable contact structure |
US5282158A (en) * | 1992-08-21 | 1994-01-25 | Micron Technology, Inc. | Transistor antifuse for a programmable ROM |
EP0592078A1 (en) * | 1992-09-23 | 1994-04-13 | Actel Corporation | Antifuse element and fabrication method |
US5308795A (en) * | 1992-11-04 | 1994-05-03 | Actel Corporation | Above via metal-to-metal antifuse |
TW232091B (ko) * | 1992-12-17 | 1994-10-11 | American Telephone & Telegraph | |
US5373169A (en) * | 1992-12-17 | 1994-12-13 | Actel Corporation | Low-temperature process metal-to-metal antifuse employing silicon link |
US5550404A (en) * | 1993-05-20 | 1996-08-27 | Actel Corporation | Electrically programmable antifuse having stair aperture |
US5300456A (en) * | 1993-06-17 | 1994-04-05 | Texas Instruments Incorporated | Metal-to-metal antifuse structure |
US5350710A (en) * | 1993-06-24 | 1994-09-27 | United Microelectronics Corporation | Device for preventing antenna effect on circuit |
JP3256603B2 (ja) * | 1993-07-05 | 2002-02-12 | 株式会社東芝 | 半導体装置及びその製造方法 |
US5498895A (en) * | 1993-07-07 | 1996-03-12 | Actel Corporation | Process ESD protection devices for use with antifuses |
US5581111A (en) * | 1993-07-07 | 1996-12-03 | Actel Corporation | Dielectric-polysilicon-dielectric antifuse for field programmable logic applications |
US5449947A (en) * | 1993-07-07 | 1995-09-12 | Actel Corporation | Read-disturb tolerant metal-to-metal antifuse and fabrication method |
US5369054A (en) * | 1993-07-07 | 1994-11-29 | Actel Corporation | Circuits for ESD protection of metal-to-metal antifuses during processing |
US5856234A (en) * | 1993-09-14 | 1999-01-05 | Actel Corporation | Method of fabricating an antifuse |
US5485031A (en) * | 1993-11-22 | 1996-01-16 | Actel Corporation | Antifuse structure suitable for VLSI application |
US5420926A (en) * | 1994-01-05 | 1995-05-30 | At&T Corp. | Anonymous credit card transactions |
US5403778A (en) * | 1994-01-06 | 1995-04-04 | Texas Instruments Incorporated | Limited metal reaction for contact cleaning and improved metal-to-metal antifuse contact cleaning method |
US5412593A (en) * | 1994-01-12 | 1995-05-02 | Texas Instruments Incorporated | Fuse and antifuse reprogrammable link for integrated circuits |
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JP3501416B2 (ja) * | 1994-04-28 | 2004-03-02 | 忠弘 大見 | 半導体装置 |
US5521440A (en) * | 1994-05-25 | 1996-05-28 | Crosspoint Solutions, Inc. | Low-capacitance, plugged antifuse and method of manufacture therefor |
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US5756367A (en) * | 1994-11-07 | 1998-05-26 | Advanced Micro Devices, Inc. | Method of making a spacer based antifuse structure for low capacitance and high reliability |
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KR100252447B1 (ko) * | 1995-06-02 | 2000-04-15 | 아르므 엠. 무센 | 융기된텅스텐플러그앤티퓨즈및제조공정 |
US5986322A (en) * | 1995-06-06 | 1999-11-16 | Mccollum; John L. | Reduced leakage antifuse structure |
US5741720A (en) * | 1995-10-04 | 1998-04-21 | Actel Corporation | Method of programming an improved metal-to-metal via-type antifuse |
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US5693556A (en) * | 1995-12-29 | 1997-12-02 | Cypress Semiconductor Corp. | Method of making an antifuse metal post structure |
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US4203123A (en) * | 1977-12-12 | 1980-05-13 | Burroughs Corporation | Thin film memory device employing amorphous semiconductor materials |
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EP0041770A3 (en) * | 1980-05-23 | 1984-07-11 | Texas Instruments Incorporated | A programmable read-only-memory element and method of fabrication thereof |
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JPH01206631A (ja) * | 1988-02-15 | 1989-08-18 | Toshiba Corp | 半導体装置の製造方法 |
JPH01241175A (ja) * | 1988-03-23 | 1989-09-26 | Seikosha Co Ltd | 非晶質シリコン薄膜トランジスタの製造方法 |
JPH02153552A (ja) * | 1988-08-23 | 1990-06-13 | Seiko Epson Corp | 半導体素子及びその製造方法 |
US4914055A (en) * | 1989-08-24 | 1990-04-03 | Advanced Micro Devices, Inc. | Semiconductor antifuse structure and method |
JPH03209867A (ja) * | 1990-01-12 | 1991-09-12 | Seiko Epson Corp | 非熔断半導体記憶装置 |
-
1991
- 1991-02-27 US US07/661,736 patent/US5100827A/en not_active Expired - Lifetime
-
1992
- 1992-01-17 TW TW081100317A patent/TW234202B/zh active
- 1992-02-20 KR KR1019920002542A patent/KR100234444B1/ko not_active IP Right Cessation
- 1992-02-21 EP EP19920301439 patent/EP0501687A3/en not_active Withdrawn
- 1992-02-26 JP JP4072979A patent/JP2642559B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US5100827A (en) | 1992-03-31 |
TW234202B (ko) | 1994-11-11 |
EP0501687A3 (en) | 1993-01-07 |
KR100234444B1 (ko) | 1999-12-15 |
JPH06169017A (ja) | 1994-06-14 |
EP0501687A2 (en) | 1992-09-02 |
JP2642559B2 (ja) | 1997-08-20 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
LAPS | Lapse due to unpaid annual fee |