TW234202B - - Google Patents

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TW234202B
TW234202B TW081100317A TW81100317A TW234202B TW 234202 B TW234202 B TW 234202B TW 081100317 A TW081100317 A TW 081100317A TW 81100317 A TW81100317 A TW 81100317A TW 234202 B TW234202 B TW 234202B
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Taiwan
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layer
window
dielectric layer
amorphous silicon
depositing
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TW081100317A
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English (en)
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At & T Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/055—Fuse

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Description

A6 B6 34202 五、發明説明（1 ) 技術頜域 本發明係相關於具有一或多個可電性程弍規劃之反熔 線的稹體電路。 發明背景 今天最精密的積體電路具有百萬個元件，並且需要複 雜的製造技術。這些技術由設計一個完整的光罩組開始： 它們通常需要較長的時間才能完成，並且實施起來成本相 當高。費用使得積體電路的生產不是大量就是高價位，但 對低成本和小量生產的電路而言，或對必須快速製造的電 路而言，我們希望能有較簡化的技術可供使罔。因此，已 有一些技術朝向不需採用傳統製造技術中使.宅的完全依客 戶設計製定光罩組的方向發展。 其中一種方法是使用標準光罩組於所有積體電路，並 且在製造完成後再針對特定用途來依客戶設計製定電路。 此方法一般使用於可程式邏輯列（p la )和許多僅謓記 憶體（ROM)。在依客戶設計成形的過程中，一個主要 步騄是選擇一個電子霉路的斷路或通路。 針對如何選擇切斷或導通電路，已發展出若干技術： 其中一種導通電路技術是在一結構上施加一個超過臨限電 壓的電壓，以將結構從一個高阻抗0 F F狀態改變到低阻 抗ON狀態。這結構稱反熔線，其類比於已知熔線從無阻 抗ON狀態改變成高阻抗OFF狀態。目前已發展出很多 製造反熔線技術。例如，可在二導電材料間使用一層非晶 本紙張尺及通用中SB家標準（CNS)甲4規格（210 X 297公* )一 ^ '一" 82.3. 40,000 (請先閲f面之注意事項再塡寫本頁) -裝. 訂_ 經濟部中喪標準局員工消費合作杜印製 34202 經濟部中喪標準局8工消费合作社印*:衣 A6 B6 ------ 五、發明説明（Δ ) 砂。當所加電壓超過臨限値時，非晶矽的晅抗穴幅地減低 。請參見例如1 9 8 4年4月1 〇日和1 9 8 6年7月8 日發佈的美國專利4 ，4 4 2 ，5 0 7和 4，5 9 9，7 0 5號，和Cook於1 9 8 6年雙極電路和 技術大會的p P 9 9〜1 0 0中所發表的有裴代表性反熔 線技術之說明。 在電路內，反熔線可執行不同功能。例如，反熔線可 包含在記憶體內儲存的資訊，或它們可用來在電路內選擇 性地連接不同的元件。應注意的是，在許多應用中，反熔 線是經一間階介電質（interlev el dielectric )來完成 一個電子電路的。用以經一間階介電質來形皎一個反熔線 的製程細節各不相同，但各製程均會將介電以層圖型化成 窗口以曝露底層材料部，然後沈積一材料（例如非晶矽） 於窗內並沈積另一傳導材料在非晶矽上。之後施加一個電 歷以程式規劃此裝置，例如，改變它的阻抗。 此製程在很多應用下是可產生適當結杲，但我們發現 ，程式電壓和洩電流隨裝置之不同而有很大的不同，並且 0 N狀態阻抗會隨時間慢地變化。在上所述製程中，很難 控制在窗口底部處之非晶矽的厚度（這是由於，例如，不 良之步驟覆蓋所造成者）。窗口通常具有一個縱橫比，例 如窗高對窗寬的比大於1:1。我們認爲這種厚度差異是 導致所述裝置在特性上產生不期望之變異的製程參數之一 ί請先閲讀背面之注龙事唄再填寫本頁> 丨裝· 訂. 本紙張尺度適用中國國家標準（CNS)甲4規格（210 X 297公釐） 82.3. 40,000 經濟部中央標準局κκ工消费合作杜印製 :.34202 A6 __ B6 五、發明説明（3 ) 發明結要- 本案描述一種積體電路的製造方法，其包括以下列步 驟來形成一反培線：在基體上形成多個圖型化導體：在圖 型化導體上沈積第一介電質層；型圖樣化介電層以形成至 少一個第一窗口，其暴露出圖型化導體的最上表面之部份 :並且在所暴露的最上層部份上形成一層非晶矽。然後以 下列步驟來繼續進行電路製造：沈積第二介電質，並且圖 型化第二介電質以形成至少一個第二窗口，其曝光非晶矽 的部份。製程中通常會有多數個第一和第二窗口。金屬至 少在一個窗口沈積，並可沈積於介電質的表面再予以圖型 化。 在最佳實施例中，是利用沈積方式來在暴露表面上形 成非晶矽，苒予以圖型化的。第一介電質應相對較薄，並 且窗口最好具有0. 5:1的縱橫比或更小。然後可藉由 在反熔線結構上施加一個超過臨限値的電壓來程式規劃反 熔線。 圖式的簡短說明 圖1〜4係根據本發明之具有反熔線結構的積體電路 在製造過程之各階段時之部份剖視圖。 爲清楚起見，所示元件均不依比例繪圖。 詳細說明 以下說明本發明的最佳實施例，並述及幾個或選實施 本紙張尺度通用中國國家揉準（CNTS)甲4规格（210 X 297公釐） 82.3. 40,000 (請先閲讀背面之注意事項再塡寫本頁) 丨裝· 訂· 34202 A6 B6 經濟部中央標準局貝工消费合作社印製 五、發明説明（4 ) 例。圖1示出基體1 、導體3、第一障層5、和第一介電 層7。基體係指在最下層並支撑其它材料的材料。因此基 缠1可以是具或不具裝置元件的矽，或一個介電質，例如 氧化或氣化较等。導趙奥型地是鋁，通常具小置其他元素 ，例如銅或矽，可利甩習知技術沈稹獲致。障層中包括— 種可防止鋁和矽相互擴散的材料。障層及其材料是本技術 領域內所已知者。在沈積障層後，再將之與鋁—起圖型化 以形成圖型化之導糖。接著沈携第一介電層7。介電層最 好由可沈積成薄層的介電質來構成。舉例而言，可選擇具 或不具摻雜質的電漿增進TEOS。 接著將第一介電層7圖型化形成窗口以至少暴露圖型 化導體的最上表面的選定部份，亦即暴露第一障層5的表 面部份。因爲介電層是薄的，故窗口能具有〇 . 5-: 1的 縱橫比或更少。如此小的縱橫比是最好的，因爲它有助於 確保後續沈積非晶矽時的均勻性。這些步驟可使用習用已 知技術來達成。所產生的結構示於圖2。 現在沈稹並圖型化非晶矽9、傳導材料1 1、和一個 第二障壁材料13層，以覆蓋圇型化導體的暴露部份。圖 3顯示所得之圖型化結構。非晶矽在〇 F F狀態具有高阻 抗。在非晶矽內包括小置，典型地少於2 0原子百分比的 雜質（例如氫）有助於增加阻抗。傳導材料1 1 ，例如鈦 或導體3的材料，是於施加程式規劃電壓時減低非晶矽阻 抗的材料。程式規劃電壓可能產生局部加熱，跟著使矽或 傳導材料擴散並形成矽化物。除了鈦外其它傳導材料亦可 (請先閲讀背面之注意事項再塡寫本頁) 裝· 訂_ 本紙張尺度迺用中國國家襟準（CNS)甲4规格（210 X 297公釐） 82.3. 40,000 Γ34202 A6 B6 選~> ,¾¾¾^料}也可位在非晶矽層的另外一邊，即層5和 9間，並且甚至可存在兩餍的傳導材料，各在非晶较層的 —邊。此外，在某些實施例中或可省略傳導材料。此情形 下圖型化導體3的材料執行傳導材料的功能。第二障層和 第一障層5具有相同功能。 再沈積一個介電層15並圖型化形成至少一個窗口， 以暴露非晶矽的選定部份。接著在窗□中或也在介電層的 最上面沈積金屬1 7。假如在最上面上有沈積的話，則將 之圖型化形成如圖4所示型式的結構。 現在對此結構略作說明。與透過窗口來沈積非晶较的 製程相比，本製程需較少非晶矽，雖然增加光罩是一個缺 點。但，本發明的反熔線的特性不會隨反熔線之不同而大 幅地樊化，並且與透過窗口來沈積矽所得的反熔線相比， 本案在程式規劃電壓上的變化較少。 熟習該行業之技術人士可立即想到其他賁施例，例如 ，圓型化之導體可爲不同裝置的元件。TE 0 S外的其它 介電質也可採用。此外，導體可爲鎢，並且可省略第一和 第二障層。 (請先Μ讀背面之注意事項再填寫本頁) -装. 订. 缰濟部中央標準局霣工消费合作杜印製 82.3. 40,000 本紙張尺度迺用中國國家缥準（CNS)甲4规格（210 X 297公董）

Claims (1)

  1. ；；34202 B7 C7 D7 六、申請專利範園 {請先閲讀背面之注意事項再項寫本頁} 1 . 一種積體電路製造方法，包括以下列步蹂來形成 一個反熔線：在基體上形成多個圖型化導體； 沈稹一個第一障層在該圖型化導體上： 在該障層上沈積一第一介電餍： 圖型化該第一介電層，以形成至少一個第一窗口，其 暴露出該障餍的最上表面的.部份： 沈積並圖型化一層非晶矽，以覆蓋該暴露部份； 沈積至少一層傳導材料，該至少一層傳導材料與所述 非晶矽相鄰；以及 在該傳導材料上沈稹第二層障層。 2 .如申請專利範園第1項之方法，尙包括以下步踝 :沈積一個第二介電層並圖型化該第二介電層，以形成至 少一個第二窗口而暴露該非晶矽的部份。 3.如申請專利範圔第2項之方法，尙包括在該至少 一個第二窗口中沈稹金屬（1 7 )的步驟。 4 .如申請專利範圔第3項之方法，尙包括在非晶矽 (9 )上施加超過臨限電壓値之電壓，以程式規劃該非晶 较（9 )的步驟。 鳗濟部中夹螵攀局霣工消费合作社印* 5.如申請專利範園第1項之方法，所述之該第一窗 具有0_ 5:1或更小的縱橫比。 本纸張人度適十··家襟準（CNS)甲4 Λ格（210 X 297公釐>
TW081100317A 1991-02-27 1992-01-17 TW234202B (zh)

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Application Number Priority Date Filing Date Title
US07/661,736 US5100827A (en) 1991-02-27 1991-02-27 Buried antifuse

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TW234202B true TW234202B (zh) 1994-11-11

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US (1) US5100827A (zh)
EP (1) EP0501687A3 (zh)
JP (1) JP2642559B2 (zh)
KR (1) KR100234444B1 (zh)
TW (1) TW234202B (zh)

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EP0501687A3 (en) 1993-01-07
KR920017258A (ko) 1992-09-26
JP2642559B2 (ja) 1997-08-20
JPH06169017A (ja) 1994-06-14
US5100827A (en) 1992-03-31
EP0501687A2 (en) 1992-09-02
KR100234444B1 (ko) 1999-12-15

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