KR920005249A - 집적된 실리콘 및 비-실리콘 반도체 장치의 제조방법 - Google Patents
집적된 실리콘 및 비-실리콘 반도체 장치의 제조방법 Download PDFInfo
- Publication number
- KR920005249A KR920005249A KR1019910014386A KR910014386A KR920005249A KR 920005249 A KR920005249 A KR 920005249A KR 1019910014386 A KR1019910014386 A KR 1019910014386A KR 910014386 A KR910014386 A KR 910014386A KR 920005249 A KR920005249 A KR 920005249A
- Authority
- KR
- South Korea
- Prior art keywords
- silicon
- semiconductor substrate
- silicon semiconductor
- silicon wafer
- integrated
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims 29
- 229910052710 silicon Inorganic materials 0.000 title claims 29
- 239000010703 silicon Substances 0.000 title claims 29
- 239000004065 semiconductor Substances 0.000 title claims 13
- 238000000034 method Methods 0.000 title claims 3
- 239000000758 substrate Substances 0.000 claims 10
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02387—Group 13/15 materials
- H01L21/02395—Arsenides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 및 제2도는 여러 단계의 제조에서 본 발명의 제1실시예를 확대시킨 단면도.
제3도는 본 발명의 제2실시예를 확대시킨 단면도.
Claims (3)
- 실리콘 웨이퍼를 제공하고, 상기 실리콘 웨이퍼에 비-실리콘 반도체 기판을 결합하고, 상기 비-실리콘 반도체 기판을 바람직한 두께로 얇게 하고, 부분적인 실리콘 웨이퍼를 노출시키기 위해 부분적인 비-실리콘 반도체 기판을 제거하는 스텝을 포함하고, 집적된 실리콘 및 비-실리콘 반도체 장치를 제조하는 방법.
- 실리콘 웨이퍼를 제공하고, 상기 실리콘 웨이퍼에 비-실리콘 반도체 기판을 결합하고, 상기 비-실리콘 반도체 기판을 바람직한 두께로 얇게 하고, 부분적인 실리콘 웨이퍼를 노출시키기 위해 부분적인 비-실리콘 반도체 기판을 제거하고, 부분적인 비-실리콘 반도체 기판이 제거되는 실리콘 웨이퍼상에서 실리콘을 선택적으로성장시키는 단계를 포함하고, 집적된 실리콘 및 비-실리콘 반도체 장치를 제조하는 방법.
- 실리콘 웨이퍼를 제공하고, 비-실리콘 반도체 기판을 실리콘 웨이퍼에 결합하고, 여기서 비-실리콘 반도체 기판이 실리콘 웨이퍼에 결합되는 표면상에서 형성된 웰을 갖고, 비-실리콘 반도체 기판을 최소한의 웰에 얇게 하는 스텝을 포함하고, 집적된 실리콘 및 비-실리콘 장치를 제조하는 방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US576,543 | 1990-08-31 | ||
US07/576,543 US5064781A (en) | 1990-08-31 | 1990-08-31 | Method of fabricating integrated silicon and non-silicon semiconductor devices |
Publications (2)
Publication Number | Publication Date |
---|---|
KR920005249A true KR920005249A (ko) | 1992-03-28 |
KR100251817B1 KR100251817B1 (ko) | 2000-05-01 |
Family
ID=24304866
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910014386A KR100251817B1 (ko) | 1990-08-31 | 1991-08-21 | 집적화된 실리콘 및 비실리콘 반도체장치의 제조방법 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5064781A (ko) |
JP (1) | JPH04298037A (ko) |
KR (1) | KR100251817B1 (ko) |
DE (1) | DE4118593C2 (ko) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR930008861B1 (ko) * | 1991-05-16 | 1993-09-16 | 재단법인 한국전자통신연구소 | 단결정 실리콘 기판상에 화합물 반도체층이 형성된 기판의 제조방법 |
DE4238137A1 (de) * | 1992-11-12 | 1994-05-19 | Ant Nachrichtentech | Verfahren zur Herstellung von Vorrichtungen mit Bauelementen |
US5346848A (en) * | 1993-06-01 | 1994-09-13 | Motorola, Inc. | Method of bonding silicon and III-V semiconductor materials |
US6250192B1 (en) * | 1996-11-12 | 2001-06-26 | Micron Technology, Inc. | Method for sawing wafers employing multiple indexing techniques for multiple die dimensions |
US6392257B1 (en) * | 2000-02-10 | 2002-05-21 | Motorola Inc. | Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same |
EP1290733A1 (en) | 2000-05-31 | 2003-03-12 | Motorola, Inc. | Semiconductor device and method for manufacturing the same |
AU2001277001A1 (en) | 2000-07-24 | 2002-02-05 | Motorola, Inc. | Heterojunction tunneling diodes and process for fabricating same |
US20020096683A1 (en) | 2001-01-19 | 2002-07-25 | Motorola, Inc. | Structure and method for fabricating GaN devices utilizing the formation of a compliant substrate |
WO2002082551A1 (en) * | 2001-04-02 | 2002-10-17 | Motorola, Inc. | A semiconductor structure exhibiting reduced leakage current |
US20020158245A1 (en) * | 2001-04-26 | 2002-10-31 | Motorola, Inc. | Structure and method for fabricating semiconductor structures and devices utilizing binary metal oxide layers |
US6992321B2 (en) * | 2001-07-13 | 2006-01-31 | Motorola, Inc. | Structure and method for fabricating semiconductor structures and devices utilizing piezoelectric materials |
US7019332B2 (en) | 2001-07-20 | 2006-03-28 | Freescale Semiconductor, Inc. | Fabrication of a wavelength locker within a semiconductor structure |
US6855992B2 (en) | 2001-07-24 | 2005-02-15 | Motorola Inc. | Structure and method for fabricating configurable transistor devices utilizing the formation of a compliant substrate for materials used to form the same |
US20030022412A1 (en) * | 2001-07-25 | 2003-01-30 | Motorola, Inc. | Monolithic semiconductor-piezoelectric device structures and electroacoustic charge transport devices |
US20030034491A1 (en) * | 2001-08-14 | 2003-02-20 | Motorola, Inc. | Structure and method for fabricating semiconductor structures and devices for detecting an object |
US20030071327A1 (en) | 2001-10-17 | 2003-04-17 | Motorola, Inc. | Method and apparatus utilizing monocrystalline insulator |
US20040012037A1 (en) * | 2002-07-18 | 2004-01-22 | Motorola, Inc. | Hetero-integration of semiconductor materials on silicon |
US20040079285A1 (en) * | 2002-10-24 | 2004-04-29 | Motorola, Inc. | Automation of oxide material growth in molecular beam epitaxy systems |
US7169619B2 (en) * | 2002-11-19 | 2007-01-30 | Freescale Semiconductor, Inc. | Method for fabricating semiconductor structures on vicinal substrates using a low temperature, low pressure, alkaline earth metal-rich process |
US6885065B2 (en) * | 2002-11-20 | 2005-04-26 | Freescale Semiconductor, Inc. | Ferromagnetic semiconductor structure and method for forming the same |
US6965128B2 (en) | 2003-02-03 | 2005-11-15 | Freescale Semiconductor, Inc. | Structure and method for fabricating semiconductor microresonator devices |
US7020374B2 (en) | 2003-02-03 | 2006-03-28 | Freescale Semiconductor, Inc. | Optical waveguide structure and method for fabricating the same |
EP2317554B1 (en) * | 2009-10-30 | 2014-04-09 | Imec | Integrated semiconductor substrate structure and method of manufacturing an integrated semiconductor substrate structure |
US8530938B2 (en) * | 2009-12-10 | 2013-09-10 | International Rectifier Corporation | Monolithic integrated composite group III-V and group IV semiconductor device and method for fabricating same |
US8912055B2 (en) | 2011-05-03 | 2014-12-16 | Imec | Method for manufacturing a hybrid MOSFET device and hybrid MOSFET obtainable thereby |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4261781A (en) * | 1979-01-31 | 1981-04-14 | International Business Machines Corporation | Process for forming compound semiconductor bodies |
JPS595649A (ja) * | 1982-07-01 | 1984-01-12 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
US4774205A (en) * | 1986-06-13 | 1988-09-27 | Massachusetts Institute Of Technology | Monolithic integration of silicon and gallium arsenide devices |
JPS63108709A (ja) * | 1986-10-25 | 1988-05-13 | Toyota Central Res & Dev Lab Inc | 半導体装置およびその製造方法 |
US4890895A (en) * | 1987-11-13 | 1990-01-02 | Kopin Corporation | Optoelectronic interconnections for III-V devices on silicon |
US4826784A (en) * | 1987-11-13 | 1989-05-02 | Kopin Corporation | Selective OMCVD growth of compound semiconductor materials on silicon substrates |
JPH01226167A (ja) * | 1988-03-07 | 1989-09-08 | Seiko Epson Corp | 半導体装置基板の製造方法 |
-
1990
- 1990-08-31 US US07/576,543 patent/US5064781A/en not_active Expired - Lifetime
-
1991
- 1991-06-06 DE DE4118593A patent/DE4118593C2/de not_active Expired - Fee Related
- 1991-08-21 KR KR1019910014386A patent/KR100251817B1/ko not_active IP Right Cessation
- 1991-08-28 JP JP3240209A patent/JPH04298037A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
JPH04298037A (ja) | 1992-10-21 |
KR100251817B1 (ko) | 2000-05-01 |
US5064781A (en) | 1991-11-12 |
DE4118593C2 (de) | 2001-04-05 |
DE4118593A1 (de) | 1992-03-05 |
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