KR910001937A - 고 전압용 ic제조방법 - Google Patents

고 전압용 ic제조방법 Download PDF

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KR910001937A
KR910001937A KR1019900008283A KR900008283A KR910001937A KR 910001937 A KR910001937 A KR 910001937A KR 1019900008283 A KR1019900008283 A KR 1019900008283A KR 900008283 A KR900008283 A KR 900008283A KR 910001937 A KR910001937 A KR 910001937A
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wafer
forming
transistor
region
oxide
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첸밍후
피. 샤프 스테벤
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존 지. 웨브
내쇼날 세미컨덕터 코포레이션
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Publication of KR910001937A publication Critical patent/KR910001937A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/012—Bonding, e.g. electrostatic for strain gauges
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/026—Deposition thru hole in mask
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/135—Removal of substrate

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)

Abstract

내용 없음

Description

고 정바용 IC제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도내지 제4도는 산화물 분리 영역의 제조 방법을 도시하는 IC 웨이퍼 부분에 대한 도시도.
제5도는 고 전압 수직형 NPN트랜지스터를 포함하는 산화물 분리 IC웨이퍼 부분에 대한 도시도.

Claims (8)

  1. 종래의 저 전압용 트랜지스터를 포함하는 반도체 웨이퍼에 고 전압용 트랜지스터를 형성시키는 제조방법에 있어서, 상기 저 전압용 트랜지스터를 제조하는데 적합한 저항을 지니는 반도체 재료의 제1웨이퍼 및 상기 제1웨이퍼의 저항율보다 대체로 낮은 저항율을 지니는 반도체 재료의 제2웨이퍼와 함께 개시하는 단계, 상기 제2웨이퍼의 한면상에 반도체 재료인 적어도 한 에피택셜층을 형성하는 단계, 상기 제1 웨이퍼 면 및 상기 제2웨이퍼인 에피택셜층면을 폴리시하여 상기 제1웨이퍼면 및 상기 제2웨이퍼인 에피택셜 층면상에 평탄하게 미러처리하는 단계, 상기 폴리시딘 면상에 있는 각각의 웨이퍼상에 산화물을 형성하는 단계, 상기 산화물로 피복된 웨이퍼면을 세척하여 상기 산화물로 피복된 웨이퍼면에 하디드로 필릭(hydrophilic)을 제공하는 단계, 상기 하이드로 필릭면을 모두 배치하여 상기 제1 및 제2웨이퍼 사이를 부착하는 단계, 상기 산화 피복물을 합착시키도록 상기 부착된 웨이퍼를 가열함으로써 상기 제1 및 제2웨이퍼를 일원화된 구조 계합시키는 단계, 상기 제1웨이퍼의 미리 결정된 두께가 남아 있을때까지 상기 제1웨이퍼의 노출면을 그라인딩하고 에칭하는 단계, 상기 제1웨이퍼를 통해 확장하고 상기 제1웨이퍼를 모두 계합하는 산화물을 통해 확장하여 상기 에피택셜층 일부를 노출시키는 상기 제1 웨이퍼의 홈을 에칭하는 단계, 상기 홈을 에피택셜층으로 데포지트된 반도체 재료로 다시 채우는 단계, 후속적인 플랜너제조 공정동안 상기 제1웨이퍼의 노출표면을 형성하는 단계, 상기 다시 채워진 반도체 재료에 고 전압용 트랜지스터를 형성하는 단계를 포함하는 제조 방법.
  2. 제1항에 있어서, 상기 적어도 하나의 에피택셜층을 형성하는 단계는 복수개의 에피택셜층을 데포지트하는 단계를 포함하는 제조방법.
  3. 제1항에 있어서, 상기 그라인딩 및 에칭 단계는 상기 제1웨이퍼의 대부분을 제거하는 제조 방법.
  4. 제3항에 있어서, 상기 제1웨이퍼의 남아있는 두께는 수 마이크론 정도인 제조 방법.
  5. 제1항에 있어서, 상기 제1웨이퍼는 산화 단계에 앞서서 산화되도록 그 도전율면을 도우핑함으로써 상기 고도 전을 면으로 제공되는 제조 방법.
  6. 제5항에 있어서, 상기 도우핑 단계는 상기 제1웨이퍼의 도우핑 도전을 형태와 동일한 도우핑 도전을 형태를 지닌 느린 확산 불순물을 포함하는 제조 방법.
  7. 제1항에 있어서, 상기 고전압 트랜지스터를 형성하는 단계는 트랜지스터 베이스 영역을 제작하도록 상기 제1웨이퍼의 최종 두께보다 작은 제1깊이까지 정반대 도전을 특성을 지니는 다시 채워진 재료내에 불순물을 확산 시키는 단계, 상기 베이스 영역을 한정하는 영역에 내재하는 베이스 영역으로 및 트랜지스터 에미터 영역을 제작한 깊이보다 얕은 길이까지 상기 다시 채워진 재료와 동일한 도전을 특성을 지니는 불순물을 확산시키는 단계. 상기 베이스 및 에미터 영역에의 접점 및 상기 제2웨이퍼에의 접점을 제공하여 콜렉터 접점을 형성하는 단계를 포함하는 제조방법.
  8. 제1항에 있어서, 상기 고전압 트랜지스터를 형성하는 단계는 트랜지스터 채널 영역을 제작하도록 상기 제1웨이퍼의 최종 두께보다 작은 제1깊이까지 상기 다시 채워진 재료내에 정반대 도전을 형태를 지니는 불순물을 확산시키는 단계, 상기 채널 영역을 한정하는 영역에 내재하는 채널 영역으로 및 트랜지스터 소오드 영역을 제작한 깊이보다 얕은 깊이까지 상기 다시 채워진 재료와 동일한 도전을 형태를 지니는 불순물을 확산시키는 단계, 채널 확산층 에지 및 소오스 확산층 사이에 실재하는 채널 영역을 병행 처리하는 게이트 산화물을 형성하는 단계, 상기 게이트 산화물상에 게이트 도전체를 형성함으로써 트랜지스터 게이트를 제공하는 단계, 상기 소오스 및 상기 상기 게이트를 한정하는 외측의 상기 채널 영역 모두에 금속접점을 형성함으로써 상기 소오스가 상기 채널에 접촉되고 단락되어 트랜지스터 백 게이트 접점과 결합된 트랜지스터 소오스를 형성하는 단계. 상기 제2웨이퍼에의 접점을 형성함으로써 트랜지스터 드레인 전극을 제공하는 단계를 포함하는 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900008283A 1989-06-06 1990-06-05 고 전압용 ic제조방법 KR910001937A (ko)

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US361,894 1989-06-06
US07/361,894 US4908328A (en) 1989-06-06 1989-06-06 High voltage power IC process

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EP (1) EP0405183A3 (ko)
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US4908328A (en) 1990-03-13
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