KR900019202A - 전자부품 탑재용 기판의 제조방법 - Google Patents

전자부품 탑재용 기판의 제조방법 Download PDF

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KR900019202A
KR900019202A KR1019900005833A KR900005833A KR900019202A KR 900019202 A KR900019202 A KR 900019202A KR 1019900005833 A KR1019900005833 A KR 1019900005833A KR 900005833 A KR900005833 A KR 900005833A KR 900019202 A KR900019202 A KR 900019202A
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South Korea
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mask
layer
base layer
metal layer
electronic component
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KR1019900005833A
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KR930004250B1 (ko
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다께시 다께야마
미쯔히로 곤도우
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다가 쥰이찌로
이비덴 가부시끼가이샤
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    • HELECTRICITY
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    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4092Integral conductive tabs, i.e. conductive parts partly detached from the substrate
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    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
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    • Y10T428/24802Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
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Abstract

내용 없음

Description

전자 부품 탑재용 기판의 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 5도는 본 발명에 따른 제조방법에 의해 만들어진 전자 부품 탑재용 기판의 일예를 보여주는 부분확대 평면도, 제 6도는 제5도의 Ⅱ-Ⅱ선을 따라 취한 단면도.

Claims (3)

  1. 금속층(11)에 대하여 기재층(12)을 일체화하고 이 기재층으로부터 상기 금속층의 소정 깊이를 노출시킴으로써 만들어지는 전자 부품 탑재용 기판(10)의 제조방법으로서, 노출부(11A)로 될 부분의 금속층과 기재층 사이에 마스크(16)를 배치하고, 그 후 상기 금속층에 대하여 상기 기재층을 일체화하는 공정과, 상기 마스크주위에 위치하는 금속층위의 기재층에 대하여 이 기재층으로부터 상기 금속층측에 레이저 광을 조사하여 상기 마스크 주위의 기재층을 절단하는 공정과, 상기 마스크 위의 기재층을 이 마스크와 동시에 제거하는 공정을 포함하고 있는 것을 특징으로 하는 전자 부품 탑재용 기판의 제조방법.
  2. 제 1항에 있어서, 상기 기재층은 유리수지 프리프레그(glass resin prepreg)로 제조 되며, 상기 금속층은 구리합금시이트로 제조되며, 상기 마스크는 수지 필름으로 제조되며, 상기 레이저광은 CO2레이저로부터 발진한것임을 특징으로 하는 전자 부품 탑재용 기판의 제조 방법.
  3. 제 1항에 있어서, 상기 기재층은 수지 시이트로 제조되며, 상기 금속층은 알루미늄판으로 제조되며, 상기 마스크는 금속박으로 제조되며, 상기 레이저광은 CO2레이저로부터 발진한 것임을 특징으로 하는 전자 부품탑재용 기판의 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900005833A 1989-05-01 1990-04-25 전자부품 탑재용 기판의 제조방법 KR930004250B1 (ko)

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GB9000550D0 (en) 1990-03-14
FR2646584A1 (fr) 1990-11-02
KR930004250B1 (ko) 1993-05-22
JPH02292846A (ja) 1990-12-04
JP2676112B2 (ja) 1997-11-12
GB2231205A (en) 1990-11-07
GB2231205B (en) 1993-08-04
DE4006063A1 (de) 1990-11-08
US5088008A (en) 1992-02-11
US5022960A (en) 1991-06-11
FR2646584B1 (fr) 1993-11-26
DE4006063C2 (de) 1994-09-15

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