KR900017160A - 하이브리드 반도체 구조 및 그 형성방법 - Google Patents

하이브리드 반도체 구조 및 그 형성방법 Download PDF

Info

Publication number
KR900017160A
KR900017160A KR1019900004476A KR900004476A KR900017160A KR 900017160 A KR900017160 A KR 900017160A KR 1019900004476 A KR1019900004476 A KR 1019900004476A KR 900004476 A KR900004476 A KR 900004476A KR 900017160 A KR900017160 A KR 900017160A
Authority
KR
South Korea
Prior art keywords
substrate
pad
layer
pads
substrates
Prior art date
Application number
KR1019900004476A
Other languages
English (en)
Other versions
KR100196242B1 (ko
Inventor
사이플러 디에테르
Original Assignee
랄프 베렌스; 위르겐 프리트만
로베르트 보쉬 게엠베하
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 랄프 베렌스; 위르겐 프리트만, 로베르트 보쉬 게엠베하 filed Critical 랄프 베렌스; 위르겐 프리트만
Publication of KR900017160A publication Critical patent/KR900017160A/ko
Application granted granted Critical
Publication of KR100196242B1 publication Critical patent/KR100196242B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/5328—Conductive materials containing conductive organic materials or pastes, e.g. conductive adhesives, inks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

내용 없음

Description

하이브리드 반도체 구조 및 그 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 캐리어 기판상에 반도테 칩을 제공하기 전의 전개 투시도.
제3도는 접속 괘드가 있는 금속화된 표면 영역온 갖고 있는 캐리어 기판의 개략 수직 단면도,
제4도는 접속 패드 또는 랜드위의 금속화된 접착 영역을 포함하는 집직 회로의 일부에 대한 수직 단면도.

Claims (27)

  1. 캐리어 플레이트 기판(11); 상기 캐리어 플레이트 기판(11)의 표면에 있는 복수의 캐리어 접속 패드(13); 반도체 칩 또는 웨이퍼 기판(10) 상기 칩 또는 웨이괴 기판(10)의 표면에 있는 복수의 칩 접속 패드(16)를 갖고 있는 하이브리도 반도체 구조 형성 방법에서, 상기 기판중 적어도 하나의 표면위에 광-경화 가능한 전기적 절연 접착제 층(30;50)을 제공하고; 상기 각각의 패드(13, 16)위에 있는 상기 층의 영역이 노출되지 않고 있는 동안 상기 접착층(30:50)을 광-마스킹 기술로 노출시켜 상기 각각의 패드위의 상기 영역내의 상기 층이 접착제로서 경화되지 않게 유지시키고; 상기 전기적 절연충의 상기 패드(13, 16)위의 상기 접착제로서 경화되지 않는 영역내로 금속 파우더를 주입시켜 상기 영역이 전기적으로 전도되게 하고; 상기 기판(11, 10)의 패드(13. 16)가 서로 나란하게 하고, 상기 적어도 한 기판의 각각의 패드위의 상기 전기적 전도 접착 영역이 다른 기판의 패드에 대향해 연결되게 상기 캐리어 플레이트 기판(11)과 상기 반도체 칩 또는 웨이퍼 기판(10)을 서로 연결시키므로써, 반도체 칩 또는 웨이퍼 기판(10)의 접속 패드(16)와 캐리어 플레이트 기판(11)의 .점속 패드(13)가 전기적으로 접속되어 캐리어 패드(13)와 칩 패드(16) 사이에 전기적 및 기계적 접속이 형성하게 하는 것을 포함하는 하이브리드 반도체 구조 형성 방법.
  2. 제1항에 있어서, 금속 파우더를 상기 패드(13, 16)위의 상기 잔여 접착 영역내로 주입시키는 단계가 조립동안 바이브레이션, 세이킹 또는 원신력 또는 압력으로 상기 파우더를 상기 영역에 제공하는 것을 포함하는 하이브리도 반도체 구조 형성 방법.
  3. 제1항에 있어서, 상기 금속 파우더는 실버 파우더를 포함하는 것.
  4. 제1항에 있어서, 상기 기판중 적어도 한 기판상에 패시베이팅 층(28, 40)을 형성하는 한편 패시베이팅 층이 없는 각각의 표면의 각 패드(13. 16)을 남기고 그후 상기 광-경화 가능한 전기직 절연 접착층을 상기 패시베이팅 층위에 제공하는 상기 단계를 실행하는 단계를 포함하는 하이브리드 반도체 형성 방법.
  5. 제1항에 있어서, 상기 기판중 적어도 하나는 각각의 기판 표면상의 상기 패드로루터 뻗어 있는 접속 라인(14, 26, 27)을 포함하며, 하이브리드 반도체 구조 헝성 방법은 각각의 표면과 각각의 접속라인에 걸쳐서 패시베이팅 층을 형성하는 한편 패시베이팅 충이 없는 각각의 패드(13, 16)를 남기고 그루 상기 광-경화가능한 전기적 절연 접착층을 패시베이팅 층위에 제공하는 상기 단계를 실행하는 단계를 포함하는 것.
  6. 제1항에 있어서. 상기 기판중 적어도 하나는 각각의 기판의 표면상의 각각의 패드로부터 뻗어 있는 접속 라인(14:26, 27)을 포함하며. 상기 광-경화가능한 전기적 절연 접착층을 제공하는 상기 단계는 상기 접속 라인 위에 상기 접착제를 제공하는 단계를 포함하는 것.
  7. 제1항에 있어서, 상기 기판의 패드들을 서로 나란하게 배열하는 단계가20μm보다 작은 배열 공차를 가지고 서로 마주보는 상기 표면과 상기패드를 일렬로 하는 단계를 포함하는 것.
  8. 제1항에 있어서, 상기 접착층(50)은 캐리어 플레이트 기판(11)에 제공되는 것.
  9. 제8항에 있어서. 상기 절연 접착층을 제공하는 상기 단계를 실행하기 전에 상기 캐리어 플레이트 기판(11)상에 패시베이팅 층(40)을 제공하는 한편 패드(13)는 패시베이트되지 않게 하는 단계 및, 반도체 칩 기판(10)의 표면을 패시베이팅 하는 한괸 그위의 패드(16)는 패시베이트 되지 않게 남기는 단계를 더 포함하는 하이브리드 반도체 구조 형성 방범
  10. 제8항에 있어서. 상기 패시베이팅 층(40)의 두께보다 큰 두께를 갖고 있는보강 재료(13')로 상기 패드(13)를 보강하는 단계를 포함하며, 상기 보강재료는 니켈, 실버, 골드중 적어도 하나로 형성되는 것.
  11. 제1항에 있어서, 상기 접착층(30)은 상기 반도체 칩 또는 웨이퍼 기판(10)상에 제공되는 것.
  12. 제11항에 있어서, 상기 접착제를 포함하는 단계를 실행하기 전에 상기 반도체 칩 또는 웨이퍼 기판(10)의 상기 패드(16)는 패시베이팅 되지 않게 남겨두는 단계 및, 상기 패시베이팅 층의 두께보다 큰 두께를 갖고 있는 보강 재료(16')로 접속 패드(16)를 보강하는 단계르 더 포함하며. 상기 보강 재료는 선택적으로 니 켈, 실버, 골드중 적어도 하나로 형성되는 것.
  13. 제1항에 있어서. 상기 전기적 절연-광-경화 가능한 접착제를 제공하는 상기 단계는 상기 접착제를 상기 캐리어 플레이트 기판(11) 및 상기 반도체 칩 또는 웨이퍼 기판(17)위에 제공하는 단계를 포함하며; 상기 노출 단계는 상기 층들중 적어도 하나의 층을 노출시키는 한편 상기 경화되지 않는 두 기판의 각 패드(13, 16)위의 영역은 남겨두는 단계를 포함하며, 상기 금속파우더 주입 단계는 상기 금속파우더를 상기 각각외 패드위의 상기 영역중 적어도 한 영역내로 주입시키는 단계를 포함하는 것.
  14. 제1항에 있어서, 상기 캐리어 플레이트 기판(11)과 상기 반도체 칩 또는 웨이퍼 기판(17)을 서로 연결하는 상기 단계는 상기 패드를 제외하고 열적으로 결합되고 전기적으로 절연되는 합성 구조를 형성하기 위해 각각의 기판의 전체 표며누이의 표면 점촉이 형성되게 상기 기판들온 연결하는 단계를 포함하는 것.
  15. 제1항에 있어서. 상기 광-경화가능한 층을 제공하는 상기 단계는 상기: 두 기판(11, 10)의 표면위에서 실행되고; 상기 노출 단계는 상기 기관중 단지 한 기판의 표면위에서 실행되는데 상기 기판중 다른 기판위에 제공된 전체 표면은 겅화 않아 끈적근적하게 남겨두며; 상기 기판들을 연결하는 상기 단계는 상기 기판들이 상기 표면과 접촉되게 연결하는 단계를 포함하며, 그러므로써 경화되지 않고 끈적끈적한 표면이 다른 기판의 경화된 표면 부분들에 접착되어 기계적 및 열적으로 결합된 합성 반도체 구조를 형성하는 것.
  16. 제1항에 있어서, 상기 패드위의 경화되지 랴은 접착 영역내로 주입된 금속 파우더의 파티클 사이즈는 1내지 5μm정도인 것.
  17. 캐리어 플레이트 기판(11) ; 상기 캐리어 플레이트 기판(11)의 표면상의 복수의 캐리어 접속 패드(13); 반도체 칩 또는 웨이퍼 기판(10); 상기 칩 또는 웨이퍼 기판(10)의 표면상외 복수의 칩 접속 패드(16)를 갖는 하이브리드 반도체 구조 형성 방법에서, 방사선 에너지에 의한 방사선에 의해 끈적끈적직한 표면과 들러붙지 않는 표면 사이에서 그 특성이 변화되는 재료의 층을 상기 기판중 적어도 한 기판의 표면위에 제공하고; 패드(13, 16) 위에는 끈적끈적한 표면을 형성하고 고 재료의 나머지 위에는 끈적거리지 않는 표면을 형성하기 위해, 상기 재료에 선택적으로 방사선을 가하고; 상기 전기적 절연층의 각각의 패드(13. 16)위의 접착제의 끈적거리는 부분내로 금속 파우더를 주입시켜 상기 끈직거리는 영역이 전기적으로 전도되게 하고 상기 기판(11. 10)의 패드(13, 16)을 서로 나란히 배열하고; 반도체 칩 또는 웨이퍼 기판(10)의 접속 패드(16)와 캐리어 풀레이트 기판(11)의 접속 패드(13)가 전기적으로 접속되게 상기 적어도 한 기판의 각각의 패드위의 전기적 전도 접착 영역이 다른 기판의 패드에 대향해 연결하기 위하여 상기 캐리어 플레이트 기판(11)과 상기 반도체 칩 또는 웨이퍼 기판(10)을 서로 연결하는 단계를 포함하여, 캐리어 패드(13)와 칩 패드 사이에 전기적 및 기계적 접속이 형성되고 상기 캐리어 플레이트 기판(11)과 상기 반도체 칩 또는 웨이퍼 기판(10)의 연결시 끈적거리는 접속이 형성되는 하이브리드 반도체 구조 형성 방법.
  18. 제1항에 있어서, 상기 접착층은 방사선 에너지에 의한 방사선으로 경화되며 경화되지 않는 상태에서는 상기 패드위에서 그 층을 통해 상기 금속 파우더가 침투될 수 있는 특성을 갖고 있는 재료로 구성되며, 그러므로써 상기 영역이 전기적으로 전도성이 되는 것.
  19. 제8항에 있어서, 상기 방사선 에너지는 자외선 빛을 포함하는 것.
  20. 캐리어 플레이트 기판(11)의 표면상의 복수의 캐리어 접속 패드(13); 반도체 칩 또는 웨이퍼 기판(10); 상기 반도체 칩 또는 웨이퍼 기판(10)의 표면상의 복수의 칩 접속 패드(16)를 갖고 있는 합성 하이브리드 반도체 구조에서, 상기 기판중 적어도 하나의 기판상의 패드(13, 16) 위에 분산된 금속 파우더에 의해 전기적으로 전도성이 되는 끈적거리는 재료층 및. 상기 기판들중 적어도 한 기판상에서 상기 패드의 영역을 제외한 그 판을 덮는 전기적 절연 재료층을 포함하며. 상기 기판들은 서로 마주보고 있으며 상기 전기적 전도성의 끈적거리는 재료에 의해 전기적으로 접속되는 상기 패드들로 서로에 대항해 연결되는 합성 하이브리드 반도체 구조.
  21. 제20항에 있어서, 경화된 절연 재료층 아래에 있는 상기 기판중 한 기판의 표면상에 형성되는 패시베이팅 층(28. 40)을 더 파함하는 합성 하이브리드 반도체 구조.
  22. 제20항에 있어서. 상기 기판중 적어도 한 기판의 표면상에 위치해 있고 상기 전기적으로 절연인 경화된 절연층 아래 배치된 접속 라인(14:26, 27)을 더 포함하는 합성 하이브리드 반도체 기판.
  23. 제22항에 있어서, 상기 기판중 적어도 한 기판의 표면위에 그리고 상기 적어도 한 기판상의 접속 라인위에 제공된 패시베이팅 층(25, 40)을 더 포함하며, 상기 경화된 절연 재료는 상기 패시베이팅 층위에 제공되는 것.
  24. 제20항에 있어서, 상기 캐리어 플레이트 기판(11)은 재료; 알루미늄 옥사이드(A12O3); 알루미늄 니트라이트(AIN); 글라스; 실리콘중 적어도 하나를 포함하는 것.
  25. 제20항에 있어서. 니켈. 실버, 골드중 적어도 하나를 포함하여 상기 패드(13, 16)위에 제공되는 보강 재료층(13', 16')을 더 포함하는 합성 하이브리드 반도체 구조.
  26. 제21항에 있어서. 니켈, 실버, 골드중 적어도 하나를 포함하며 상기 패턴(13, 16)위에 제공되어 상기 패시베이팅 층 위로 뻗어 있는 보강 재료층(13', 10')을 포함하는 합성 하이브리드 반도체 구조.
  27. 제20항에 있어서. 상기 기판상의 복수의 패드는 단지 20μm까지의 공차를 갖는 간격을 갖고 있는 것
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900004476A 1989-04-05 1990-04-02 하이브리드 반도체 구조 체 및 그 제조 방법 KR100196242B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE3910910 1989-04-05
DE3910910.0 1989-04-05
DE452.110 1989-12-14
US07/452,110 US5068714A (en) 1989-04-05 1989-12-14 Method of electrically and mechanically connecting a semiconductor to a substrate using an electrically conductive tacky adhesive and the device so made

Publications (2)

Publication Number Publication Date
KR900017160A true KR900017160A (ko) 1990-11-15
KR100196242B1 KR100196242B1 (ko) 1999-06-15

Family

ID=25879520

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900004476A KR100196242B1 (ko) 1989-04-05 1990-04-02 하이브리드 반도체 구조 체 및 그 제조 방법

Country Status (4)

Country Link
US (1) US5068714A (ko)
JP (1) JP2871800B2 (ko)
KR (1) KR100196242B1 (ko)
DE (1) DE4008624A1 (ko)

Families Citing this family (81)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5611140A (en) * 1989-12-18 1997-03-18 Epoxy Technology, Inc. Method of forming electrically conductive polymer interconnects on electrical substrates
US5074947A (en) * 1989-12-18 1991-12-24 Epoxy Technology, Inc. Flip chip technology using electrically conductive polymers and dielectrics
US5866951A (en) * 1990-10-12 1999-02-02 Robert Bosch Gmbh Hybrid circuit with an electrically conductive adhesive
DE4032397A1 (de) * 1990-10-12 1992-04-16 Bosch Gmbh Robert Verfahren zur herstellung einer hybriden halbleiterstruktur und nach dem verfahren hergestellte halbleiterstruktur
JP2940269B2 (ja) * 1990-12-26 1999-08-25 日本電気株式会社 集積回路素子の接続方法
US5265329A (en) * 1991-06-12 1993-11-30 Amp Incorporated Fiber-filled elastomeric connector attachment method and product
US5225966A (en) * 1991-07-24 1993-07-06 At&T Bell Laboratories Conductive adhesive film techniques
US5140286A (en) * 1991-08-02 1992-08-18 Motorola, Inc. Oscillator with bias and buffer circuits formed in a die mounted with distributed elements on ceramic substrate
FR2684804B1 (fr) * 1991-12-06 1994-01-28 Thomson Csf Dispositif de montage de circuits integres monolithiques hyperfrequences a tres large bande.
JP2512258B2 (ja) * 1992-03-11 1996-07-03 松下電器産業株式会社 シ―ト給送装置
US5266833A (en) * 1992-03-30 1993-11-30 Capps David F Integrated circuit bus structure
US5434524A (en) * 1992-09-16 1995-07-18 International Business Machines Corporation Method of clocking integrated circuit chips
US5383787A (en) * 1993-04-27 1995-01-24 Aptix Corporation Integrated circuit package with direct access to internal signals
US5413489A (en) * 1993-04-27 1995-05-09 Aptix Corporation Integrated socket and IC package assembly
DE4319965C3 (de) 1993-06-14 2000-09-14 Emi Tec Elektronische Material Verfahren zur Herstellung eines Gehäuses mit elektromagnetischer Abschirmung
DE4327560A1 (de) * 1993-08-17 1995-02-23 Hottinger Messtechnik Baldwin Verfahren zum Kontaktieren von Leiterbahnanordnungen und Kontaktanordnung
DE4339786C5 (de) * 1993-11-18 2004-02-05 Emi-Tec Elektronische Materialien Gmbh Verfahren zur Herstellung einer Anordung zur Wärmeableitung
US5543585A (en) * 1994-02-02 1996-08-06 International Business Machines Corporation Direct chip attachment (DCA) with electrically conductive adhesives
US5750002A (en) * 1994-10-04 1998-05-12 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Method for fabricating piezoelectric polymer acoustic sensors
US6093970A (en) * 1994-11-22 2000-07-25 Sony Corporation Semiconductor device and method for manufacturing the same
JPH08167630A (ja) * 1994-12-15 1996-06-25 Hitachi Ltd チップ接続構造
DE19518659A1 (de) * 1995-05-20 1996-11-21 Bosch Gmbh Robert Verfahren zum Verbinden eines elektrischen Anschlußes eines unverpackten IC-Bauelements mit einer Leiterbahn auf einem Substrat
KR0172000B1 (ko) * 1995-08-11 1999-05-01 이대원 전도성 잉크를 이용한 반도체 패키지용 기판의 제조방법
CA2156941A1 (en) * 1995-08-21 1997-02-22 Jonathan H. Orchard-Webb Method of making electrical connections to integrated circuit
US5744383A (en) * 1995-11-17 1998-04-28 Altera Corporation Integrated circuit package fabrication method
US5842273A (en) * 1996-01-26 1998-12-01 Hewlett-Packard Company Method of forming electrical interconnects using isotropic conductive adhesives and connections formed thereby
US5956601A (en) * 1996-04-25 1999-09-21 Kabushiki Kaisha Toshiba Method of mounting a plurality of semiconductor devices in corresponding supporters
US5741430A (en) * 1996-04-25 1998-04-21 Lucent Technologies Inc. Conductive adhesive bonding means
US5717246A (en) * 1996-07-29 1998-02-10 Micron Technology, Inc. Hybrid frame with lead-lock tape
JPH10303352A (ja) * 1997-04-22 1998-11-13 Toshiba Corp 半導体装置および半導体装置の製造方法
US6143396A (en) * 1997-05-01 2000-11-07 Texas Instruments Incorporated System and method for reinforcing a bond pad
US5920037A (en) * 1997-05-12 1999-07-06 International Business Machines Corporation Conductive bonding design for metal backed circuits
WO1999000842A1 (en) * 1997-06-26 1999-01-07 Hitachi Chemical Company, Ltd. Substrate for mounting semiconductor chips
US6260264B1 (en) * 1997-12-08 2001-07-17 3M Innovative Properties Company Methods for making z-axis electrical connections
US20070102827A1 (en) * 1997-12-08 2007-05-10 3M Innovative Properties Company Solvent Assisted Burnishing of Pre-Underfilled Solder-Bumped Wafers for Flipchip Bonding
US6118080A (en) * 1998-01-13 2000-09-12 Micron Technology, Inc. Z-axis electrical contact for microelectronic devices
US6137063A (en) * 1998-02-27 2000-10-24 Micron Technology, Inc. Electrical interconnections
US6300231B1 (en) * 1998-05-29 2001-10-09 Tessera Inc. Method for creating a die shrink insensitive semiconductor package and component therefor
US6139661A (en) 1998-10-20 2000-10-31 International Business Machines Corporation Two step SMT method using masked cure
US6891110B1 (en) 1999-03-24 2005-05-10 Motorola, Inc. Circuit chip connector and method of connecting a circuit chip
US7157507B2 (en) 1999-04-14 2007-01-02 Allied Photochemical, Inc. Ultraviolet curable silver composition and related method
US6290881B1 (en) 1999-04-14 2001-09-18 Allied Photochemical, Inc. Ultraviolet curable silver composition and related method
US6230400B1 (en) * 1999-09-17 2001-05-15 George Tzanavaras Method for forming interconnects
US6767577B1 (en) 1999-10-06 2004-07-27 Allied Photochemical, Inc. Uv curable compositions for producing electroluminescent coatings
AU1819001A (en) 1999-10-06 2001-05-10 Uv Specialties, Inc. Uv curable compositions for producing electroluminescent coatings
US6500877B1 (en) 1999-11-05 2002-12-31 Krohn Industries, Inc. UV curable paint compositions and method of making and applying same
US6509389B1 (en) * 1999-11-05 2003-01-21 Uv Specialties, Inc. UV curable compositions for producing mar resistant coatings and method for depositing same
US6805917B1 (en) 1999-12-06 2004-10-19 Roy C. Krohn UV curable compositions for producing decorative metallic coatings
MXPA02005257A (es) * 1999-12-06 2003-09-22 Slidekote Inc Composiciones curables por uv.
MXPA02005287A (es) 1999-12-06 2004-04-21 Krohn Ind Inc Composiciones curables por uv para producir revestimientos de pintura de capas multiples.
JP2001185845A (ja) * 1999-12-15 2001-07-06 Internatl Business Mach Corp <Ibm> 電子部品の製造方法及び該電子部品
MXPA02006735A (es) * 2000-01-13 2002-10-11 Uv Specialties Inc Composiciones ferromagneticas que se pueden curar con luz uv.
WO2001051567A1 (en) 2000-01-13 2001-07-19 Uv Specialties, Inc. Uv curable transparent conductive compositions
JP2001217279A (ja) * 2000-02-01 2001-08-10 Mitsubishi Electric Corp 高密度実装装置
EP1126517B1 (en) * 2000-02-09 2007-01-17 Interuniversitair Micro-Elektronica Centrum Method for flip-chip assembly of semiconductor devices using adhesives
JP3781610B2 (ja) * 2000-06-28 2006-05-31 株式会社東芝 半導体装置
DE10046296C2 (de) 2000-07-17 2002-10-10 Infineon Technologies Ag Elektronisches Chipbauteil mit einer integrierten Schaltung und Verfahren zu seiner Herstellung
AU2001293252A1 (en) 2000-09-06 2002-03-22 Allied Photochemical, Inc. Uv curable silver chloride compositions for producing silver coatings
US7323499B2 (en) 2000-09-06 2008-01-29 Allied Photochemical, Inc. UV curable silver chloride compositions for producing silver coatings
CA2332190A1 (en) 2001-01-25 2002-07-25 Efos Inc. Addressable semiconductor array light source for localized radiation delivery
JP2004530249A (ja) * 2001-06-08 2004-09-30 シーゲイト テクノロジー エルエルシー Ｚ軸導電性接着フィルムを使用したヘッド・ジンバル・アセンブリのプリント回路板への取付け
US7158350B1 (en) * 2002-11-05 2007-01-02 Hutchinson Technology Incorporated Ground interconnects
US6946628B2 (en) 2003-09-09 2005-09-20 Klai Enterprises, Inc. Heating elements deposited on a substrate and related method
US7462936B2 (en) 2003-10-06 2008-12-09 Tessera, Inc. Formation of circuitry with modification of feature height
US7495179B2 (en) 2003-10-06 2009-02-24 Tessera, Inc. Components with posts and pads
US8207604B2 (en) * 2003-12-30 2012-06-26 Tessera, Inc. Microelectronic package comprising offset conductive posts on compliant layer
US7709968B2 (en) * 2003-12-30 2010-05-04 Tessera, Inc. Micro pin grid array with pin motion isolation
JP4712633B2 (ja) * 2005-08-04 2011-06-29 株式会社リコー 自動原稿搬送装置
US7928549B2 (en) * 2006-09-19 2011-04-19 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit devices with multi-dimensional pad structures
EP2637202A3 (en) 2007-09-28 2014-03-12 Tessera, Inc. Flip chip interconnection with etched posts on a microelectronic element joined to etched posts on a substrate by a fusible metal and corresponding manufacturing method
US20100044860A1 (en) * 2008-08-21 2010-02-25 Tessera Interconnect Materials, Inc. Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer
US8330272B2 (en) 2010-07-08 2012-12-11 Tessera, Inc. Microelectronic packages with dual or multiple-etched flip-chip connectors
US8580607B2 (en) 2010-07-27 2013-11-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
US20120068342A1 (en) * 2010-09-16 2012-03-22 Lee Kevin J Electrically conductive adhesive for temporary bonding
US8853558B2 (en) 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
JP5912616B2 (ja) * 2012-02-08 2016-04-27 株式会社ジェイデバイス 半導体装置及びその製造方法
CN103474401B (zh) * 2012-06-06 2016-12-14 欣兴电子股份有限公司 载板结构与芯片封装结构及其制作方法
TWI532100B (zh) * 2012-08-22 2016-05-01 國家中山科學研究院 三維半導體電路結構及其製法
US9633971B2 (en) 2015-07-10 2017-04-25 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
CN110544674A (zh) * 2018-05-28 2019-12-06 浙江清华柔性电子技术研究院 芯片集成结构

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3303393A (en) * 1963-12-27 1967-02-07 Ibm Terminals for microminiaturized devices and methods of connecting same to circuit panels
US3292240A (en) * 1963-08-08 1966-12-20 Ibm Method of fabricating microminiature functional components
US3465209A (en) * 1966-07-07 1969-09-02 Rca Corp Semiconductor devices and methods of manufacture thereof
DE1627762B2 (de) * 1966-09-17 1972-11-23 Nippon Electric Co. Ltd., Tokio Verfahren zur Herstellung einer Halbleitervorrichtung
US3795047A (en) * 1972-06-15 1974-03-05 Ibm Electrical interconnect structuring for laminate assemblies and fabricating methods therefor
DE2330161A1 (de) * 1973-06-08 1974-12-19 Minnesota Mining & Mfg Verbesserte schaltkreise und verfahren zu deren herstellung
US4069791A (en) * 1976-10-01 1978-01-24 E. I. Du Pont De Nemours And Company Automatic toning device
US4164005A (en) * 1977-09-02 1979-08-07 Sprague Electric Company Solid electrolyte capacitor, solderable terminations therefor and method for making
US4234626A (en) * 1978-02-01 1980-11-18 E. I. Du Pont De Nemours And Company Producing printed circuits by conjoining metal powder images
US4157407A (en) * 1978-02-13 1979-06-05 E. I. Du Pont De Nemours And Company Toning and solvent washout process for making conductive interconnections
US4172547A (en) * 1978-11-02 1979-10-30 Delgrande Donald J Method for soldering conventionally unsolderable surfaces
US4411980A (en) * 1981-09-21 1983-10-25 E. I. Du Pont De Nemours And Company Process for the preparation of flexible circuits
JPS59195837A (ja) * 1983-04-21 1984-11-07 Sharp Corp Ｌｓｉチツプボンデイング方法
US4469777A (en) * 1983-12-01 1984-09-04 E. I. Du Pont De Nemours And Company Single exposure process for preparing printed circuits
US4631111A (en) * 1984-11-27 1986-12-23 E. I. Du Pont De Nemours And Company Dichromic process for preparation of conductive circuit
US4572764A (en) * 1984-12-13 1986-02-25 E. I. Du Pont De Nemours And Company Preparation of photoformed plastic multistrate by via formation first
JPS6290938A (ja) * 1985-10-17 1987-04-25 Matsushita Electric Ind Co Ltd 半導体装置
US4720740A (en) * 1985-11-26 1988-01-19 Clements James R Electronic device including uniaxial conductive adhesive and method of making same
US4667401A (en) * 1985-11-26 1987-05-26 Clements James R Method of making an electronic device using an uniaxial conductive adhesive
US4868637A (en) * 1985-11-26 1989-09-19 Clements James R Electronic device including uniaxial conductive adhesive and method of making same
JPS63293894A (ja) * 1987-05-26 1988-11-30 Makuro Eng:Kk 印刷配線板の製造方法

Also Published As

Publication number Publication date
DE4008624C2 (ko) 1992-04-16
JPH0318040A (ja) 1991-01-25
DE4008624A1 (de) 1990-10-11
US5068714A (en) 1991-11-26
KR100196242B1 (ko) 1999-06-15
JP2871800B2 (ja) 1999-03-17

Similar Documents

Publication Publication Date Title
KR900017160A (ko) 하이브리드 반도체 구조 및 그 형성방법
US4902857A (en) Polymer interconnect structure
KR100203030B1 (ko) 반도체 디바이스 및 그 제조방법과 반도체 칩을 실장하기 위한 가요성 막
US6239980B1 (en) Multimodule interconnect structure and process
US3903590A (en) Multiple chip integrated circuits and method of manufacturing the same
CA1229155A (en) High density lsi package for logic circuits
JP2596960B2 (ja) 接続構造
EP0660383B1 (en) Electronic device package
US5353498A (en) Method for fabricating an integrated circuit module
US6544428B1 (en) Method for producing a multi-layer circuit board using anisotropic electro-conductive adhesive layer
US7288437B2 (en) Conductive pattern producing method and its applications
US20100155126A1 (en) Fine wiring package and method of manufacturing the same
DE102010000407B4 (de) Halbleiter-Package mit einem aus Metallschichten bestehenden Band und Verfahren zum Herstellen eines derartigen Halbleiter-Package
WO1990013991A1 (en) Method of grounding an ultra high density pad array chip carrier
JP3891678B2 (ja) 半導体装置
US6207550B1 (en) Method for fabricating bump electrodes with a leveling step for uniform heights
US6528889B1 (en) Electronic circuit device having adhesion-reinforcing pattern on a circuit board for flip-chip mounting an IC chip
JPH05500733A (ja) 印刷配線板複合構造体
DE10133571B4 (de) Elektronisches Bauteil und Verfahren zu seiner Herstellung
JP3819483B2 (ja) 半導体装置
JPH0583187B2 (ko)
JP2663649B2 (ja) マルチチップ実装方法
Fillion et al. Plastic encapsulated MCM technology for high volume, low cost electronics
JPH0363813B2 (ko)
JPS6468935A (en) Face-down bonding of semiconductor integrated circuit device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20030128

Year of fee payment: 5

LAPS Lapse due to unpaid annual fee