KR900006866A - 컴퓨터 시스템 아키덱처 - Google Patents

컴퓨터 시스템 아키덱처 Download PDF

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Publication number
KR900006866A
KR900006866A KR1019890015285A KR890015285A KR900006866A KR 900006866 A KR900006866 A KR 900006866A KR 1019890015285 A KR1019890015285 A KR 1019890015285A KR 890015285 A KR890015285 A KR 890015285A KR 900006866 A KR900006866 A KR 900006866A
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KR
South Korea
Prior art keywords
bus
master
slave
coupled
computer system
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Application number
KR1019890015285A
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English (en)
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KR920008458B1 (ko
Inventor
티이 슈바이처 폴
엘 캐럴 마이클
Original Assignee
원본미기재
엔 시이 아아르 코오포레이션
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Publication of KR900006866A publication Critical patent/KR900006866A/ko
Application granted granted Critical
Publication of KR920008458B1 publication Critical patent/KR920008458B1/ko

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)

Abstract

내용 없음

Description

컴퓨터 시스템 아키덱처
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 범용 모듈식 계층 다중 버스 컴퓨터 아키텍처를 개략적으로 나타낸 도면.
제 2 도는 궤환 형태로 배열된 프로세서 장치 모듈들을 개략적으로 나타낸 도면.
제 3 도는 고장 방지 메모리 시스템이나 연장 데이타 베이스 시스템을 실행하도록 형성된 프로세서 장치 모듈들을 개략적으로 나타낸 도면.

Claims (3)

  1. 마스터 버스 및 이 마스터 버스와 거의 동일한 슬테이브 버스 ; 상기 마스터 버스를 통해 제어 및 통신하도록 연결된 마스터 프로세서 ; 상기 슬레이브 버스를 통해 제어 및 통신하도록 연결된 슬레이브 프로세서 ; 상기 마스터 버스를 통해 통신하도록 연결된 마스터 램(RAM) ; 상기 마스터 버스와 상기 슬레이브 버스 사이에 연결되어 비동기 제어신호들을 상기 마스터 및 슬레이브 프로세서들 사이에 전송하는 인터페이스 제어기 수단 ; 제 1 포트에서 연결되어 상기 마스터 버스를 통해 통신하고 제 2 포트에서 연결되어 상기 슬레이브 버스를 통해 통신하는 공유 이중 포트 램 ; 및 상기 마스터 버스, 상기 슬레이브 버스, 및 상기 공유 이중 포트 램과 연결되어 공유 이중 포트 램 이용요구 신호들을 수신하고 상기 공유 이중 포트 램을 통한 제어를 조정하는 공유 램 제어기 수단 ; 의 조합으로 구성되는 프로세서들 및 프로세서 관련 버스들을 포함하는 컴퓨터 시스템 아키텍처.
  2. 제 1 항에 있어서, 상기 공유 이중 포트 램이 양 포트에서부터 동시에 변지지정가능한 컴퓨터 시스템 아키텍처.
  3. 제 2 항에 있어서, 상기 마스터 및 슬레이브 버스들이 도선수, 도선에 의한 기능성, 및 도선에 의한 신호내용에 있어서 거의 동일한 컴퓨터 시스템 아키텍처.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890015285A 1988-10-24 1989-10-23 컴퓨터 시스템 구조체 KR920008458B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US261537 1988-10-24
US261,537 1988-10-24
US07/261,537 US4912633A (en) 1988-10-24 1988-10-24 Hierarchical multiple bus computer architecture

Publications (2)

Publication Number Publication Date
KR900006866A true KR900006866A (ko) 1990-05-09
KR920008458B1 KR920008458B1 (ko) 1992-09-30

Family

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Application Number Title Priority Date Filing Date
KR1019890015285A KR920008458B1 (ko) 1988-10-24 1989-10-23 컴퓨터 시스템 구조체

Country Status (5)

Country Link
US (1) US4912633A (ko)
EP (1) EP0366361B1 (ko)
JP (1) JPH02127759A (ko)
KR (1) KR920008458B1 (ko)
DE (1) DE68927626T2 (ko)

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Also Published As

Publication number Publication date
JPH02127759A (ja) 1990-05-16
EP0366361B1 (en) 1997-01-08
DE68927626T2 (de) 1997-09-04
EP0366361A2 (en) 1990-05-02
US4912633A (en) 1990-03-27
EP0366361A3 (en) 1991-03-20
DE68927626D1 (de) 1997-02-20
KR920008458B1 (ko) 1992-09-30

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