WO1988004451A1

WO1988004451A1 - Bus control system in a multiple-processor system

Info

Publication number: WO1988004451A1
Application number: PCT/JP1987/000920
Authority: WO
Inventors: Mitsuo Kurakake; Jiro Kinoshita
Original assignee: Fanuc Ltd
Priority date: 1986-12-01
Filing date: 1987-11-27
Publication date: 1988-06-16
Also published as: JPS63138448A

Abstract

A bus control system in a multiple-processor system constituted by connecting, via address and data buses (51, 52, 53), modules (1, 2) that contain devices such as processors (15, 25) and input/output devices. The modules (1, 2) are equipped with bus arbitration control circuits (14, 24), and two-way bus switches (11, 12, 13; 21, 22, 23). The bus control system is further equipped with control signal lines (61, 62, 63) for bus arbitration connecting the bus arbitration control circuits (14, 24). The two-way bus switches are opened and closed under the control of the bus arbitration control circuits and, as a result, the processors are connected in parallel or through pipelines.

Description

Description Bus control method in a multi-sensor system

The present invention relates to a bus control method between a plurality of modules in a multi-processor system. North

Landscape technology

As a conventional bus control method that supports multiple processors, a parallel bus method or a pipeline method is generally used.

The parallel bus method is a method in which multiple processors and input / output (I / O) devices are connected to the same bus, and one processor becomes a bus master by one bus arbitration control circuit. With the right, you can access memory etc. in other modules. Here, the module includes a processor and a device or an input / output device, and is a unit constituting a part of the system.

The pipeline method divides instruction processing into multiple stages that include processors, and executes processing between stages in a single processor in parallel.

However, in the parallel bus system described above, a certain processor can access a device controlled by the same bus, unless otherwise specified. So it ’s very versatile, t

There is only one bus master that can be a bus master at the same time, and the more processors there are, and the more frequently the bus is accessed, the higher the noise utilization . Therefore, if too many processors are connected to the same bus, the use of the bus degrades the efficiency of the broker.

In the pipeline method, as the number of processors is increased and the average of individual processes is increased, the efficiency increases, but since the data bus is only between the processors, the data flow must be changed. But not very versatile.

The present invention has been made in view of the above problems. Orchid of invention

An object of the present invention is to make it possible to control the connection of a module that houses a port processor to either a parallel bus system or a pipeline system, thereby maintaining the versatility in processor processing. And to increase the efficiency of the processor.

In the present invention, a bus in a multiprocessor system including a plurality of modules each having a processor and a device controlled by the processor, and an address and a data bus connecting the modules. A control system, wherein each of the modules includes a bus arbitration control circuit, a first bidirectional bus switch which is connected between two addresses and a data bus connected to the module, and Connected between one of the address and data buses and the processor and the device. A second bidirectional bus switch, and a third bidirectional bus switch connected between the other of the two addresses and the data bus and the processor and the device. The method includes a bus arbitration control signal line connecting between the bus arbitration control circuits, wherein the bus arbitration control circuit in each module controls opening and closing of a bidirectional bus switch, and the processor is A bus arbitration control circuit of another module is controlled through the bus arbitration control circuit and the bus arbitration control signal line, and processors and devices in each module are connected in parallel with respect to the address and the data bus. Alternatively, a bus control method in a multi-processor system with a pipeline connection is provided. BRIEF DESCRIPTION OF THE FIGURES

Fig. 1 is a block diagram showing the parallel bus system in the conventional example.

FIG. 2 is a block diagram illustrating a conventional pipeline method.

FIG. 3 is a circuit diagram illustrating a bus control method in a multiplex processor system as one embodiment of the present invention.

FIG. 4 is a diagram for explaining a control example in the embodiment, and FIG. 5 is a diagram for explaining another control example similar to FIG. BEST MODE FOR CARRYING OUT THE INVENTION

Prior to the description of the embodiments of the present invention, a conventional multi-processor The bus control method in the stem with reference to FIGS. 1 and 2 will be described ₀

Fig. 1 shows a parallel bus system for pre-arrest. The parallel bus method is a method in which a plurality of processors (PR0C.) 73 and 74 and input / output devices (I / O) 75 are connected in parallel to the same bus (BUS) 71. The bus arbitration control circuit (BUS ARB. C0NT) 72 allows a certain processor to acquire the right to become a bus master and access memory of other module meat.

As shown in FIG. 2, the pipeline method restricts the flow of processing to one direction, that is, the processor (PRO) 81, the node (BUS) 83, and the processor ( PR0C.) 8 2, and a bus (BUS) 8 4 direction, which enables parallel processing of multiple processors. .

FIG. 3I shows a circuit diagram of a module and a bus of a bus control method in a multiprocessor system as one embodiment of the present invention. _ ノ ·

The module (HOB.) 1 includes bidirectional bus switches 11, 12, and 13, a bus arbitration control circuit (BUS ARB.CONT J 14,... And a processor (PR0C.) 15). .

The module 2 includes the bidirectional bus switches 21, 22, and 23, the bus arbitration control circuit 24, the processor 25, and the like, in substantially the same manner as the module 1. Here, components with the same name are the same.

Address and data bus 51 from the good side is a bilateral bus Connected to one end of switches 11 and 12. A lower address and a data bus 52 are connected to the other end of the bus switch 11 and one end of the bus switch 13. The other ends of the bus switches 12 and 13 are connected to each other and to the processor 15 and other devices. The bus arbitration control circuit 14 is connected to the bus arbitration control signal line 61 from the upper side and the bus arbitration control signal line 62 from the lower side, and the bus switches 11, 12, and 13 Control the opening and closing of The processor 15 can control the bus arbitration control circuit 2 and the like of other modules via the bus arbitration control circuit 14 and the bus arbitration control signal line.

The description of module 1 above can be applied to other modules as well. The distinction between the superior and inferior sides of the module is given for convenience of explanation.

To perform bus surroundings similar to the conventional parallel bus system, the bus switches 11 and 21 may be closed, and the bus switches 12 or 13 and 22 or 23 may be closed. In the case of the conventional pipeline connection, the bus switches 11 and 21 are opened and the bus switches 12, 13, 22, and 23 are closed.

A control example of the embodiment of the present invention will be described with reference to FIG. In the module in the figure, description of components other than the bus switch is omitted. In this example, there is a case where there are a plurality of processors, and data is exchanged between the adjacent processors. That is, when module 1 accesses a device in module 2, the bus arbitration control signal line The bus arbitration control signal transmitted by the bus 2 indicates that the bus 52 is empty, and operates the bus switches 13 and 2 of the module 1 and the bus switches 22 of the module 2 so that the arrows 6 5 And a bus 52 between modules 1 and 2 is activated. The operations of the bus switches 13 and 22 are controlled by the bus arbitration control circuit of L. At this time, the access of the module 3 to the device in the module 2 is Is not possible because module 1 is accessed by module 1, but module 3 can access module 4 and beyond (see arrow 6S). In this example, modules 1 and 2 and modules 3 and 4 are connected by pipeline. The bus 53 and the signal line 63 are equivalent to being cut off as indicated by the X 'mark.

The fifth drawing shows another control example in the embodiment. In this example, there are multiple processors, and data is exchanged between non-adjacent processors. When module 1 accesses the device in module 3, the bus arbitration control signal (signal on signal line 62) between modules 1 and 2 causes the bus 52 between modules 1 and 2 to be connected. When it is empty, the bus switch 13 of module 1 is operated, and the simple bus arbitration control signal of module 2 and 3 (signal of signal line 63) is used for the simple bus of module 2 and 3. Knowing that 5 3 is empty, it operates the bus switch 21 of module 2 and the bus switch 32 of module 3 to Activate the bus between modules 1 and 2 and between modules 2 and 3 (see arrows 67). The operations of the bus switches 13, 21, and 32 are controlled by the respective bus arbitration control circuits of the modules 1, 2, and 3.

In addition, the bus arbitration control circuit of each module has an address map that identifies which module will be the slave if the bus request originates from another module. It has a locking mechanism (not shown). For example, the bus arbitration control circuit 24 of the module 2 determines whether a request for the module 2 or a request for the module 3 or later is issued when a bus request is issued from the module 1. Judge, and operate the bus switch 22 or 21. The address mapping mechanism is for this identification.

Claims

Scope of Claim West

1. A bus control method in a multiprocessor system including a plurality of modules each having a processor and a device controlled by the processor, and an address and a data bus connecting the modules. ,

Each of the modules includes a bus arbitration control circuit, a first bidirectional bus switch that is connected between two addresses and a data bus, which are connected to the module, and a bus arbitration control circuit, One and a second bidirectional bus switch which is easily connected to the processor and the device; and the other of the two address and data buses and the processor and the device. A third bidirectional bus switch connected to the bus, and the bus arbitration control signal line that connects the bus arbitration control circuits with the bus arbitration control circuit;

The bus arbitration control circuit in each module controls opening and closing of a bidirectional bus switch, and the processor communicates with another module via the bus arbitration control circuit and the bus arbitration control signal line. A bus control method in a multi-processor system in which a bus arbitration control circuit is controlled and a processor and a device in each module are connected in parallel or in a pipeline with respect to an address and a data bus.

2. closing the first bi-directional bus switch and either the second or the third bi-directional bus switch, thereby connecting the aperture sensor and the device in parallel, and 2. The method according to claim 1, wherein the bidirectional bus switch is opened, and the second and third bidirectional bus switches are closed, whereby the processor and the device are connected by a pipeline. Bus control method