WO1996010904A3 - Digital signal processor - Google Patents

Digital signal processor Download PDF

Info

Publication number
WO1996010904A3
WO1996010904A3 PCT/US1995/013386 US9513386W WO9610904A3 WO 1996010904 A3 WO1996010904 A3 WO 1996010904A3 US 9513386 W US9513386 W US 9513386W WO 9610904 A3 WO9610904 A3 WO 9610904A3
Authority
WO
WIPO (PCT)
Prior art keywords
processor
digital signal
signal processor
external
access
Prior art date
Application number
PCT/US1995/013386
Other languages
French (fr)
Other versions
WO1996010904A2 (en
Inventor
Douglas Garde
Ronnin J Yee
Mark A Valley
Steven L Cox
Aaron H Gorius
Original Assignee
Analog Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/317,313 external-priority patent/US5634076A/en
Priority claimed from US08/317,744 external-priority patent/US5685005A/en
Application filed by Analog Devices Inc filed Critical Analog Devices Inc
Priority to AU41941/96A priority Critical patent/AU4194196A/en
Priority to JP8512740A priority patent/JPH10509540A/en
Priority to EP95940520A priority patent/EP0784823A2/en
Publication of WO1996010904A2 publication Critical patent/WO1996010904A2/en
Publication of WO1996010904A3 publication Critical patent/WO1996010904A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284—Multiple user address space allocation, e.g. using different base addresses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
    • G06F15/7846—On-chip cache and off-chip main memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
    • G06F15/7857—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers) using interleaved memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)
  • Multi Processors (AREA)

Abstract

A monolithic digital signal processor includes a core processor for performing digital signal computations, an I/O processor for controlling external access to and from the digital signal processor through an external port, first and second memory banks for storing instructions and data for the digital signal computations, and first and second buses interconnecting the core processor, the I/O processor and the memory banks. The core processor and the I/O processor access the memory banks on the first bus without interference on different clock phases of a clock cycle. The internal memory and the I/O processor of the digital signal processor are assigned to a region of a global memory space, which facilitates multiprocessing configurations. In a multiprocessor system, each digital signal processor is assigned a processor ID. The digital signal processor includes a bus arbitration circuit for controlling access to an external bus through the external port. The digital signal processor may include one or more serial ports and one or more link ports for point-to-point communication with external devices. A DMA controller controls DMA transfers through the external port, the serial ports and the link ports.
PCT/US1995/013386 1994-10-04 1995-10-04 Digital signal processor WO1996010904A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU41941/96A AU4194196A (en) 1994-10-04 1995-10-04 Digital signal processor
JP8512740A JPH10509540A (en) 1994-10-04 1995-10-04 Digital signal processor
EP95940520A EP0784823A2 (en) 1994-10-04 1995-10-04 Digital signal processor

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US31789194A 1994-10-04 1994-10-04
US31788694A 1994-10-04 1994-10-04
US08/317,744 1994-10-04
US08/317,886 1994-10-04
US08/317,891 1994-10-04
US08/317,313 US5634076A (en) 1994-10-04 1994-10-04 DMA controller responsive to transition of a request signal between first state and second state and maintaining of second state for controlling data transfer
US08/317,313 1994-10-04
US08/317,744 US5685005A (en) 1994-10-04 1994-10-04 Digital signal processor configured for multiprocessing

Publications (2)

Publication Number Publication Date
WO1996010904A2 WO1996010904A2 (en) 1996-04-18
WO1996010904A3 true WO1996010904A3 (en) 1996-09-12

Family

ID=27502141

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1995/013386 WO1996010904A2 (en) 1994-10-04 1995-10-04 Digital signal processor

Country Status (4)

Country Link
EP (1) EP0784823A2 (en)
JP (1) JPH10509540A (en)
AU (1) AU4194196A (en)
WO (1) WO1996010904A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7240144B2 (en) * 2004-04-02 2007-07-03 Arm Limited Arbitration of data transfer requests

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1990007154A1 (en) * 1988-12-15 1990-06-28 Flashpoint Computer Corporation Memory address mechanism in a distributed memory architecture
EP0427407A2 (en) * 1989-11-03 1991-05-15 Compaq Computer Corporation Parallel port with direct memory access capabilities
EP0537072A1 (en) * 1991-10-09 1993-04-14 Lg Electronics Inc. Method and system for interfacing PC TO CD-Rom drives
EP0540206A2 (en) * 1991-10-15 1993-05-05 International Business Machines Corporation Information handling apparatus allowing direct memory access
EP0560020A2 (en) * 1992-03-13 1993-09-15 International Business Machines Corporation Digital signal processing function appearing as hardware FIFO

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1990007154A1 (en) * 1988-12-15 1990-06-28 Flashpoint Computer Corporation Memory address mechanism in a distributed memory architecture
EP0427407A2 (en) * 1989-11-03 1991-05-15 Compaq Computer Corporation Parallel port with direct memory access capabilities
EP0537072A1 (en) * 1991-10-09 1993-04-14 Lg Electronics Inc. Method and system for interfacing PC TO CD-Rom drives
EP0540206A2 (en) * 1991-10-15 1993-05-05 International Business Machines Corporation Information handling apparatus allowing direct memory access
EP0560020A2 (en) * 1992-03-13 1993-09-15 International Business Machines Corporation Digital signal processing function appearing as hardware FIFO

Non-Patent Citations (8)

* Cited by examiner, † Cited by third party
Title
"DSP TOOLS: NAVIGATING THE HARDWARE/SOFTWARE INTERFACE", COMPUTER DESIGN, vol. 33, no. 11, 1 October 1994 (1994-10-01), pages 69/70, 72, 74, 76, 78, 80, 82, 84, 86, 88, XP000477330 *
ANONYMOUS: "Distributed Process Bulletin Board.", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 33, no. 10A, March 1991 (1991-03-01), NEW YORK, US, pages 1 - 5, XP000109937 *
BEDU J Y: "LES DSPS ANALOG DEVICES (2)", ELECTRONIQUE RADIO PLANS, no. 545, 1 April 1993 (1993-04-01), pages 57 - 64, XP000368051 *
BREWER J E ET AL: "A monolithic processing subsystem", IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, PART B: ADVANCED PACKAGING, AUG. 1994, USA, ISSN 1070-9894, XP002009148 *
BREWER J E ET AL: "A single-chip digital signal processing subsystem", 1994 PROCEEDINGS. SIXTH ANNUAL IEEE INTERNATIONAL CONFERENCE ON WAFER SCALE INTEGRATION (CAT. NO.94CH3412-4), PROCEEDINGS OF 1994 INTERNATIONAL CONFERENCE ON WAFER SCALE INTEGRATION (ICWSI), SAN FRANCISCO, CA, USA, 19-21 JAN. 1994, ISBN 0-7803-1850-1, 1994, NEW YORK, NY, USA, IEEE, USA, pages 265 - 272, XP002009149 *
COUNIHAN T ET AL: "On-chip integrated memories in DSP (distributed signal processing) architectures", ELEKTRONIK, 14 JUNE 1994, GERMANY, vol. 43, no. 12, ISSN 0013-5658, pages 98 - 102, 104, 106, XP000464141 *
GARDE D ET AL: "A 120MFLOP DIGITAL SIGNAL PROCESSOR FOR MULTI-PROCESSING APPLICATIONS", GOVERNMENT MICROCIRCUIT APPLICATIONS CONFERENCE, 1 November 1993 (1993-11-01), pages 67 - 70, XP000567621 *
SIMAR JR R ET AL: "FLOATING-POINT PROCESSORS JOIN FORCES IN PARALLEL PROCESSING ARCHITECTURES", IEEE MICRO, vol. 12, no. 4, 1 August 1992 (1992-08-01), pages 60 - 69, XP000293560 *

Also Published As

Publication number Publication date
JPH10509540A (en) 1998-09-14
WO1996010904A2 (en) 1996-04-18
EP0784823A2 (en) 1997-07-23
AU4194196A (en) 1996-05-02

Similar Documents

Publication Publication Date Title
KR930008771B1 (en) Ic incoporating processor and memory
KR970705087A (en) Integrated Circuit with Multiple Functions Sharing Multiple Internal Signal Buses According to Distributed Bus Access and Control Arbitration
EP0834816A3 (en) Microprocessor architecture capable of supporting multiple heterogenous processors
DE60139109D1 (en) Common program memory for multi-core DSP devices
CA2050129A1 (en) Dynamic bus arbitration with grant sharing each cycle
WO2001035246A3 (en) Cache memory system and method for a digital signal processor
US6892266B2 (en) Multicore DSP device having coupled subsystem memory buses for global DMA access
US5944806A (en) Microprocessor with versatile addressing
WO1996010904A3 (en) Digital signal processor
JPS589461B2 (en) multiprocessor system
JPS5650451A (en) Multiaccess system of multimicrocomputer
JPH0343804A (en) Sequence controller
EP0114839B1 (en) A high performance multi-processor system
JPS59218532A (en) Bus connecting system
JPS645341B2 (en)
JPS59183455A (en) Multi-computer system
JPS59229662A (en) Common memory control circuit
JPH0114616B2 (en)
JP2612715B2 (en) Address bus controller
JPS62127962A (en) Microcomputer
JP2001022710A (en) System with plural bus controllers
JPH01154272A (en) Multiprocessor device
JP2001155006A (en) Bus control circuit and microcomputer system using the same
JPS62224855A (en) Data processor
JPS63236153A (en) Storage device

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AL AM AT AU BB BG BR BY CA CH CN CZ DE DK EE ES FI GB GE HU IS JP KE KG KP KR KZ LK LR LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK TJ TM TT UA UG UZ VN

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): KE MW SD SZ UG AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN ML MR NE SN TD TG

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
AK Designated states

Kind code of ref document: A3

Designated state(s): AL AM AT AU BB BG BR BY CA CH CN CZ DE DK EE ES FI GB GE HU IS JP KE KG KP KR KZ LK LR LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK TJ TM TT UA UG UZ VN

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): KE MW SD SZ UG AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN ML MR NE SN TD TG

WWE Wipo information: entry into national phase

Ref document number: 1995940520

Country of ref document: EP

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

WWP Wipo information: published in national office

Ref document number: 1995940520

Country of ref document: EP

WWR Wipo information: refused in national office

Ref document number: 1995940520

Country of ref document: EP

WWW Wipo information: withdrawn in national office

Ref document number: 1995940520

Country of ref document: EP