AU4194196A - Digital signal processor - Google Patents

Digital signal processor

Info

Publication number
AU4194196A
AU4194196A AU41941/96A AU4194196A AU4194196A AU 4194196 A AU4194196 A AU 4194196A AU 41941/96 A AU41941/96 A AU 41941/96A AU 4194196 A AU4194196 A AU 4194196A AU 4194196 A AU4194196 A AU 4194196A
Authority
AU
Australia
Prior art keywords
digital signal
signal processor
processor
digital
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU41941/96A
Inventor
Steven L Cox
Douglas Garde
Aaron H Gorius
Mark A Valley
Ronnin J Yee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Analog Devices Inc
Original Assignee
Analog Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/317,744 external-priority patent/US5685005A/en
Priority claimed from US08/317,313 external-priority patent/US5634076A/en
Application filed by Analog Devices Inc filed Critical Analog Devices Inc
Publication of AU4194196A publication Critical patent/AU4194196A/en
Abandoned legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284Multiple user address space allocation, e.g. using different base addresses
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7842Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
    • G06F15/7846On-chip cache and off-chip main memory
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7842Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
    • G06F15/7857Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers) using interleaved memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)
  • Multi Processors (AREA)
AU41941/96A 1994-10-04 1995-10-04 Digital signal processor Abandoned AU4194196A (en)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US31789194A 1994-10-04 1994-10-04
US31788694A 1994-10-04 1994-10-04
US08/317,744 US5685005A (en) 1994-10-04 1994-10-04 Digital signal processor configured for multiprocessing
US08/317,313 US5634076A (en) 1994-10-04 1994-10-04 DMA controller responsive to transition of a request signal between first state and second state and maintaining of second state for controlling data transfer
US317744 1994-10-04
US317886 1994-10-04
PCT/US1995/013386 WO1996010904A2 (en) 1994-10-04 1995-10-04 Digital signal processor
US317313 1999-05-24
US317891 2002-12-12

Publications (1)

Publication Number Publication Date
AU4194196A true AU4194196A (en) 1996-05-02

Family

ID=27502141

Family Applications (1)

Application Number Title Priority Date Filing Date
AU41941/96A Abandoned AU4194196A (en) 1994-10-04 1995-10-04 Digital signal processor

Country Status (4)

Country Link
EP (1) EP0784823A2 (en)
JP (1) JPH10509540A (en)
AU (1) AU4194196A (en)
WO (1) WO1996010904A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7240144B2 (en) * 2004-04-02 2007-07-03 Arm Limited Arbitration of data transfer requests

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5117350A (en) * 1988-12-15 1992-05-26 Flashpoint Computer Corporation Memory address mechanism in a distributed memory architecture
EP0427407A3 (en) * 1989-11-03 1993-03-10 Compaq Computer Corporation Parallel port with direct memory access capabilities
KR940003319B1 (en) * 1991-10-09 1994-04-20 주식회사 금성사 Interface method and system between pc and cd-rom drive
US5381538A (en) * 1991-10-15 1995-01-10 International Business Machines Corp. DMA controller including a FIFO register and a residual register for data buffering and having different operating modes
JPH0683578A (en) * 1992-03-13 1994-03-25 Internatl Business Mach Corp <Ibm> Method for controlling processing system and data throughput

Also Published As

Publication number Publication date
EP0784823A2 (en) 1997-07-23
WO1996010904A2 (en) 1996-04-18
JPH10509540A (en) 1998-09-14
WO1996010904A3 (en) 1996-09-12

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