JPS5839360A - Memory access system - Google Patents

Abstract

PURPOSE:To send data to another processor without useless data transfer, by allowing respective plural processors to access both their local memories and local memories of the opposite connected processors. CONSTITUTION:A control processor 200 has a memory 210 as a local memory, and processors 201-204 also have memories 211-214 as local memories. The processors 201 and 202, and 203 and 204 are connected mutually through an interexchange channel 220. Consequently, the processor 201 handles the memory 212 connected externally to the memory 211, and the processor 202 handles the memory 212 and external memory 211. similarly, the processor 203 handles the memories 213 and 214, and the processor 204 handles the memories 214 and 213. Therefore, for example, when the processor 201 is to send data to the processor 202, the data are written at the upper side of the memory map of the processor 202 as they are only by writing the data at the lower side of the memory map of the processor 201, i.e. in the memory 212.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory addressing system for connecting a plurality of microprocessors and memories and for data transfer between nine multiprocessors.

Conventional ▼In the case of multi-processors, there is a method for connecting the processors as shown in Figure 1, for example. Each processor 101, 102, 109 has a memory 11, respectively.
1, 121, 112, 122, 119
, 129, the processor 101 has a memory 111
, 121 accesses the memory 112, 12
2, the processor 109 can access the memories 119 and 129. In addition, the relay circuits 121, 122, and 129 are relay circuits 13 for transferring data and switching routes.
They are interconnected through 0. For example, when processor 101 attempts to send data to processor 102,
access? 101 stores data in memory 121;
Next, a command is issued to the relay circuit 130 to transfer data from the memory 121 to the memory 122. The relay circuit 130 transfers the data from the memory 121 to the memory 122, and when the Grossener 102 is notified of this, the processor 102 means that the processor 101 has also received the data.

As explained above, in conventional methods, the connection between processors and memory is fixed at one-to-one, so when one processor tries to access the memory of another processor,
data must be transferred, and the same data must be transferred to the memories of different processors (memories 121 and 12 in the above description).
2). However, the existence of the same data is wasteful and inconvenient, and data transfer is time consuming and wasteful.

In view of the above drawbacks, the present invention provides a memory access method for data transfer between multiple processors that does not involve data transfer and therefore does not require the same data to reside in different memories.

Next, details of the present invention will be explained using examples.

The second @I is a configuration diagram of an embodiment of the present invention. There are four processors below, and one control processor that controls the entire system.
An example will be explained in which there is a machine.

In Figure 2, the control processor tCP 200 is a memo IJ m
210, and each processor Ps 201 and Ps 20
2, Ps 203.

P, 204 is the memory ff1l 211, 1
111212, ml 213.

-214 as local memory. In addition, each processor 201, 202, SiO2, 2Q4 is a middle 1
It is connected via the circuit 220, but in the @2 diagram, P, 20
1 and P! 202 and P, 203 and P, and 2G4 are connected. As a result, the memory address space visible from each processor 7 becomes as shown in FIG. That is, p12
01 can see his local memory m, 211 and mR 212 connected to the outside, and P, 202 can see his local memory m, 212 and external nt 1211. Similarly, pm203 is 5213 and m, and 214°Pa204 is m
4214 and m5213 are visible. Also, note the control processor tcp2oo that controls the whole thing! J m 210 raw memory connected to each processor 201 , 202 , 203 , 204 ff1l 211 , mt 212
, m5213, and m4214 are visible.

Data transfer using the above connection is performed, for example, as follows. It is assumed that the connections shown in Figure 2 result in a memory map as shown in Figure 3. The topmost area in the memory map of FIG. 3, that is, the memory area for the processor Pi, is a local memory, so it is always visible even if the connection method is different. However, the memory visible in the lower area is different depending on the 'i# connection method. Therefore, for example, when processor P 201 wants to send data to processor P 202, the lower part of the memory map of processor P 201,
When data is written into the 9th memory 1n, 212, it is written to the upper part of the memory map of the processor P, 202 as is.

As described above, each processor is connected to the memory area visible on the lower side by the relay circuit 220 and becomes the memory of the other party, and can send data to the other party without unnecessary data transfer.

On the other hand, the control processor CP 200 needs to transfer data with all the processors, so in addition to its own local memory m 210, it also uses the memory of all the processors!
J211, mB212, mB213,
m4214 is now visible.

The relay circuit 220 can be easily realized using, for example, a bus connection and an address translation table method. Of course, other methods such as a switch method may also be used.

In the above example, the address space of P is 10m! However, like CP, it can also be designated as 10 towns.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a conventional multiprocessor connection method, and FIG. 2 is a diagram showing an embodiment of the connection method according to the present invention.
FIG. 3 is a diagram showing a memory map of each processor according to the present invention. 200......Control processors 201 to 204...Processor 210...Memory 21
1-214...Local memory agent Patent attorney Noriyuki Chika (and 1 other person) Figure 3 CPPf/'z ^ P4

Claims (2)

[Claims] (1) In a single multiprocessor that interconnects multiple processors and multiple memories, the four processors Pl can access both the local memory area and the local memory rnJ of the connected partner processor Pj. . (2) A control processor that integrally controls a plurality of processors is capable of accessing the local memory of all other processors in addition to the local memory of the control processor. method.