JPS5839360A - Memory access system - Google Patents

Memory access system

Info

Publication number
JPS5839360A
JPS5839360A JP13612781A JP13612781A JPS5839360A JP S5839360 A JPS5839360 A JP S5839360A JP 13612781 A JP13612781 A JP 13612781A JP 13612781 A JP13612781 A JP 13612781A JP S5839360 A JPS5839360 A JP S5839360A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
processor
memory
memories
handles
processors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13612781A
Inventor
Yutaka Hitai
Kazuhide Iwata
Shigeru Koyanagi
Shigeki Shibayama
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/17Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Abstract

PURPOSE:To send data to another processor without useless data transfer, by allowing respective plural processors to access both their local memories and local memories of the opposite connected processors. CONSTITUTION:A control processor 200 has a memory 210 as a local memory, and processors 201-204 also have memories 211-214 as local memories. The processors 201 and 202, and 203 and 204 are connected mutually through an interexchange channel 220. Consequently, the processor 201 handles the memory 212 connected externally to the memory 211, and the processor 202 handles the memory 212 and external memory 211. similarly, the processor 203 handles the memories 213 and 214, and the processor 204 handles the memories 214 and 213. Therefore, for example, when the processor 201 is to send data to the processor 202, the data are written at the upper side of the memory map of the processor 202 as they are only by writing the data at the lower side of the memory map of the processor 201, i.e. in the memory 212.
JP13612781A 1981-09-01 1981-09-01 Memory access system Pending JPS5839360A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13612781A JPS5839360A (en) 1981-09-01 1981-09-01 Memory access system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13612781A JPS5839360A (en) 1981-09-01 1981-09-01 Memory access system

Publications (1)

Publication Number Publication Date
JPS5839360A true true JPS5839360A (en) 1983-03-08

Family

ID=15167932

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13612781A Pending JPS5839360A (en) 1981-09-01 1981-09-01 Memory access system

Country Status (1)

Country Link
JP (1) JPS5839360A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0240354A1 (en) * 1986-04-04 1987-10-07 The British Petroleum Company p.l.c. Memory Architecture for multiprocessor computers
JPS6320652A (en) * 1986-07-15 1988-01-28 Fujitsu Ltd Processor synchronizing system
EP0261034A2 (en) * 1986-09-18 1988-03-23 Digital Equipment Corporation Massively parallel array processing system
US5146606A (en) * 1986-09-18 1992-09-08 Digital Equipment Corporation Systems for interconnecting and configuring plurality of memory elements by control of mode signals
US5230079A (en) * 1986-09-18 1993-07-20 Digital Equipment Corporation Massively parallel array processing system with processors selectively accessing memory module locations using address in microword or in address register
US5469158A (en) * 1992-04-20 1995-11-21 Sumitomo Electric Industries, Ltd. Apparatus for correcting the detected heading of a vehicle

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0240354A1 (en) * 1986-04-04 1987-10-07 The British Petroleum Company p.l.c. Memory Architecture for multiprocessor computers
WO1987006039A1 (en) * 1986-04-04 1987-10-08 The British Petroleum Company P.L.C. Memory architecture for multiprocessor computers
JPS6320652A (en) * 1986-07-15 1988-01-28 Fujitsu Ltd Processor synchronizing system
EP0261034A2 (en) * 1986-09-18 1988-03-23 Digital Equipment Corporation Massively parallel array processing system
US5146606A (en) * 1986-09-18 1992-09-08 Digital Equipment Corporation Systems for interconnecting and configuring plurality of memory elements by control of mode signals
US5230079A (en) * 1986-09-18 1993-07-20 Digital Equipment Corporation Massively parallel array processing system with processors selectively accessing memory module locations using address in microword or in address register
US5469158A (en) * 1992-04-20 1995-11-21 Sumitomo Electric Industries, Ltd. Apparatus for correcting the detected heading of a vehicle

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