DE68927626T2 - Hierarchisches Mehrfachbus-Computersystem - Google Patents

Hierarchisches Mehrfachbus-Computersystem

Info

Publication number
DE68927626T2
DE68927626T2 DE68927626T DE68927626T DE68927626T2 DE 68927626 T2 DE68927626 T2 DE 68927626T2 DE 68927626 T DE68927626 T DE 68927626T DE 68927626 T DE68927626 T DE 68927626T DE 68927626 T2 DE68927626 T2 DE 68927626T2
Authority
DE
Germany
Prior art keywords
computer system
multiple bus
bus computer
hierarchical multiple
hierarchical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68927626T
Other languages
English (en)
Other versions
DE68927626D1 (de
Inventor
Paul T Schweizer
Michael L Carroll
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR International Inc
Original Assignee
NCR International Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR International Inc filed Critical NCR International Inc
Application granted granted Critical
Publication of DE68927626D1 publication Critical patent/DE68927626D1/de
Publication of DE68927626T2 publication Critical patent/DE68927626T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
DE68927626T 1988-10-24 1989-10-19 Hierarchisches Mehrfachbus-Computersystem Expired - Fee Related DE68927626T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/261,537 US4912633A (en) 1988-10-24 1988-10-24 Hierarchical multiple bus computer architecture

Publications (2)

Publication Number Publication Date
DE68927626D1 DE68927626D1 (de) 1997-02-20
DE68927626T2 true DE68927626T2 (de) 1997-09-04

Family

ID=22993763

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68927626T Expired - Fee Related DE68927626T2 (de) 1988-10-24 1989-10-19 Hierarchisches Mehrfachbus-Computersystem

Country Status (5)

Country Link
US (1) US4912633A (de)
EP (1) EP0366361B1 (de)
JP (1) JPH02127759A (de)
KR (1) KR920008458B1 (de)
DE (1) DE68927626T2 (de)

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DE4209760A1 (de) * 1992-03-23 1993-09-30 Siemens Ag Verfahren zum Verändern des Inhaltes eines Programmspeichers eines Slave-Rechners
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EP0855654B1 (de) * 1992-06-17 2004-04-07 Texas Instruments Incorporated Hierarchisches Verbindungsverfahren und -gerät
KR950003880B1 (ko) * 1992-07-02 1995-04-20 한국전기통신공사 버스 인터페이스 방식에 의한 집중관리 시스템
JPH08500687A (ja) * 1992-08-10 1996-01-23 モノリシック・システム・テクノロジー・インコーポレイテッド ウェハ規模の集積化のためのフォルトトレラントな高速度のバス装置及びバスインタフェース
US5511165A (en) * 1992-10-23 1996-04-23 International Business Machines Corporation Method and apparatus for communicating data across a bus bridge upon request
JPH0827773B2 (ja) * 1992-10-23 1996-03-21 インターナショナル・ビジネス・マシーンズ・コーポレイション データ経路を使用可能にする方法、装置およびデータ処理システム
JP3524110B2 (ja) * 1992-11-06 2004-05-10 株式会社ルネサステクノロジ マイクロコンピュータシステム
US5542055A (en) * 1993-05-28 1996-07-30 International Business Machines Corp. System for counting the number of peripheral buses in each hierarch connected to primary bus for creating map of peripheral buses to locate peripheral devices
IT1260848B (it) * 1993-06-11 1996-04-23 Finmeccanica Spa Sistema a multiprocessore
US5657482A (en) * 1993-08-24 1997-08-12 Micron Electronics, Inc. Automatic clock speed sensing system for determining the number of states needed for a time-dependent operation by sensing clock frequency
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DE4331618A1 (de) * 1993-09-17 1995-03-23 Philips Patentverwaltung Kommunikationselement für ein hierarchisches Verwaltungsnetz
CA2145106C (en) * 1994-04-22 1999-08-24 Abhaya Asthana Intelligent memory-based input/output system
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WO1996013776A1 (en) * 1994-10-31 1996-05-09 Intel Corporation M & a for exchanging data, status, and commands over a hierarchical serial bus assembly using communication packets
US5615404A (en) * 1994-10-31 1997-03-25 Intel Corporation System having independently addressable bus interfaces coupled to serially connected multi-ported signal distributors generating and maintaining frame based polling schedule favoring isochronous peripherals
US5621901A (en) * 1994-10-31 1997-04-15 Intel Corporation Method and apparatus for serial bus elements of an hierarchical serial bus assembly to electrically represent data and control states to each other
US5623610A (en) * 1994-10-31 1997-04-22 Intel Corporation System for assigning geographical addresses in a hierarchical serial bus by enabling upstream port and selectively enabling disabled ports at power on/reset
DE19529718C2 (de) * 1995-08-11 2000-03-23 Siemens Ag Auf einer Baugruppe angeordnete Pufferschaltung
US5969538A (en) 1996-10-31 1999-10-19 Texas Instruments Incorporated Semiconductor wafer with interconnect between dies for testing and a process of testing
KR100197407B1 (ko) * 1995-12-28 1999-06-15 유기범 전전자 교환기에 있어서 프로세서들간 통신버스구조
GB2308902B (en) * 1996-01-04 2000-03-29 Motorola Inc Peripheral module and microprocessor system
US5805835A (en) * 1996-07-15 1998-09-08 Micron Electronics, Inc. Parallel architecture computer system and method
US6044207A (en) * 1997-03-21 2000-03-28 Adaptec, Inc. Enhanced dual port I/O bus bridge
US6115823A (en) * 1997-06-17 2000-09-05 Amphus, Inc. System and method for task performance based dynamic distributed power management in a computer system and design method therefor
US6112316A (en) * 1997-12-03 2000-08-29 Micron Electronics, Inc. System for use of bus parking states to communicate diagnostic information
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US7085866B1 (en) * 2002-02-19 2006-08-01 Hobson Richard F Hierarchical bus structure and memory access protocol for multiprocessor systems
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US9934179B2 (en) * 2015-02-17 2018-04-03 Mediatek Inc. Wafer-level package with at least one input/output port connected to at least one management bus
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JPS6388669A (ja) * 1986-10-01 1988-04-19 Matsushita Graphic Commun Syst Inc Ｃｐｕ間通信装置

Also Published As

Publication number Publication date
EP0366361B1 (de) 1997-01-08
US4912633A (en) 1990-03-27
JPH02127759A (ja) 1990-05-16
KR920008458B1 (ko) 1992-09-30
DE68927626D1 (de) 1997-02-20
EP0366361A3 (de) 1991-03-20
KR900006866A (ko) 1990-05-09
EP0366361A2 (de) 1990-05-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: V. BEZOLD & SOZIEN, 80799 MUENCHEN

8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee