GB8828488D0 - Computer bus structure for multiple processors - Google Patents

Computer bus structure for multiple processors

Info

Publication number
GB8828488D0
GB8828488D0 GB888828488A GB8828488A GB8828488D0 GB 8828488 D0 GB8828488 D0 GB 8828488D0 GB 888828488 A GB888828488 A GB 888828488A GB 8828488 A GB8828488 A GB 8828488A GB 8828488 D0 GB8828488 D0 GB 8828488D0
Authority
GB
United Kingdom
Prior art keywords
multiple processors
bus structure
computer bus
computer
processors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB888828488A
Other versions
GB2225882A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
FLARE TECHNOLOGY Ltd
Original Assignee
FLARE TECHNOLOGY Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by FLARE TECHNOLOGY Ltd filed Critical FLARE TECHNOLOGY Ltd
Priority to GB8828488A priority Critical patent/GB2225882A/en
Publication of GB8828488D0 publication Critical patent/GB8828488D0/en
Publication of GB2225882A publication Critical patent/GB2225882A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Bus Control (AREA)
GB8828488A 1988-12-06 1988-12-06 Computer bus structure for multiple processors Withdrawn GB2225882A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB8828488A GB2225882A (en) 1988-12-06 1988-12-06 Computer bus structure for multiple processors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8828488A GB2225882A (en) 1988-12-06 1988-12-06 Computer bus structure for multiple processors

Publications (2)

Publication Number Publication Date
GB8828488D0 true GB8828488D0 (en) 1989-01-05
GB2225882A GB2225882A (en) 1990-06-13

Family

ID=10648064

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8828488A Withdrawn GB2225882A (en) 1988-12-06 1988-12-06 Computer bus structure for multiple processors

Country Status (1)

Country Link
GB (1) GB2225882A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5655131A (en) * 1992-12-18 1997-08-05 Xerox Corporation SIMD architecture for connection to host processor's bus

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2076191B (en) * 1978-12-26 1983-06-02 Honeywell Inf Systems Improvements in or relating to terminal systems for data processors
CA1266524A (en) * 1983-08-30 1990-03-06 Shinobu Arimoto Image processing system
US4598356A (en) * 1983-12-30 1986-07-01 International Business Machines Corporation Data processing system including a main processor and a co-processor and co-processor error handling logic
US4695945A (en) * 1985-02-28 1987-09-22 International Business Machines Corporation Processor I/O and interrupt filters allowing a co-processor to run software unknown to the main processor
GB2173929A (en) * 1985-04-20 1986-10-22 Itt Ind Ltd Computer systems

Also Published As

Publication number Publication date
GB2225882A (en) 1990-06-13

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)