GB2173929A - Computer systems - Google Patents

Abstract

A computer system of the kind in which a number of computer peripherals (DEVICE I...N) are connected to a central processor unit by means of a common bus line over which they can send "Interrupt" signals to the CPU to interrupt the operation of the latter where necessary and ensure that none of the inputs from any of the peripherals is lost before it can be processed. In order to simplify and speed up the operation of such a system by avoiding the necessity to interrogate all the peripherals in turn to find out whether an interrupt signal is being initiated by them, circuitry is provided to enable multiple compatible peripheral controllers to deliver bus vectored (i.e. identified) interrupts on a single interrupt request line (INT-). <IMAGE>

Description

SPECIFICATION Computer systems This invention relates to computer systems and in particular to computer systems of the kind in which a number of computer peripheral controllers are connected to a central processor unit (CPU) by means of a common parallel bus over which they can send "Interrupt" signals to the CPU to interrupt the operation of the latter when necessary. An example of such a system is that known as MULTIBUS I, to which the invention is particularly applicable.

An object of the invention is to simplify and speed up the operation of such a system by avoiding the necessity to interrogate all the peripherals in turn to find out whether an interrupt signal is being initiated by them.

According to the invention in its broadest aspect, a computer system of the kind referred to is provided with means in the form of electric circuits adapted to enable multiple bus compatible peripheral controllers to deliver bus vectored (i.e. identified) interrupts on a single interrupt request line.

An embodiment of the invention will now be described by way of example with reference to the accompanying drawing in the form of a circuit block diagram.

The interrupt handling hardware for Multibus I compatible devices is usually based on the Intel (RTM)i 8259 Programmable Interrupt Controller (PIC). Only 8 bus vectored interrupts are possible as there are only eight interrupt request inputs into the master PIC (on the CPU board) anbd eight Multibus interrupt request lines.

The invention overcomes this restriction by pipe-lining (i.e. in serial mode) the Bus Vectored Interrupts (BVI) on a single Multibus interrupt line. Two modifications to the standard system are required:~ (a) special circuitry on each of the peripheral controllers using this system.

(b) special circuitry on the Multibus card cage backplane.

Considering first the standard system, the interrupt request output from the i8259 PIC on each of the peripheral controllers is connected to the Multibus interrupt request line.

When the PlC's interrupt request is activated the PlC's interrupt output renders the Multibus interrupt request line active. The CPU responds by sending an acknowledgement with the address identifying the interrupting PIC.

The PIC detecting its own identity address releases the vector held in its vector register.

The CPU reads the vector and enters the appropriate software subroutine.

Referring now to the embodiment of the invention shown in the drawing, the interrupt request output from the peripheral controller i8259 PIC is connected to the on-board arbitration circuitry rather than to the Multibus interrupt request line. The arbitration circuitry senses the state of the Multibus interrupt request line selected to pipe-line the interrupts.

Its output is connected via the P2 connecter to the parallel priority resolver accommodated on the system's card cage backplane PCB.

The resolver's corresponding output is connected back to the peripheral controller and acts as an interrupt request. It activates the Multibus interrupt request line via the open collector gate and enables the Multibus address lines to the PIC for its indentification.

When the interrupt is initiated the following sequence of events can occur (a) No interrupt in service If there is no interrupt in service originated by any of the peripheral controllers using the pipe-lining system e.g. their common Multibus interrupt request line is inactive, the arbitration circuitry passes the interrupt request to the priority resolver. Its output drives the Multibus interrupt request line active and locks the arbitration circuitry. From then on the further sequence is that of the standard system as described earlier. The end of the interrupt performed by the software resets the PIC interrupt request output which in turn deactivates the arbitration circuitry, priority resolver and the Multibus interrupt request line (b) Interrupt in service The common Multibus interrupt request line is active. The arbitration circuitry detecting this condition blocks the PlC's interrupt request output and does not pass the request to the priority resolver. The interrupt becomes "pipe-lined" until the current interrupt cycle is finished and the Multibus interrupt request line is deactivated.

(c) Multiple interrupt requests If there is no interrupt in service (i.e. Multibus interrupt request line is inactive) and multiple interrupt requests occur they are all passed by their arbitration circuitry to the parallel priority resolver. In this case only, the highest priority one will be enabled and allowed to activate the Multibus interrupt request line. Once this becomes active, all other requests are made to "back-off" and queue.

Claims (2)

1. A computer system of the kind referred to provided with means in the form of electric circuits adapted to enable multiple bus compatible peripheral controllers to deliver bus vectored (i.e. identified) interrupts on a single interrupt request line.

2. A computer system substantially as described with reference to the accompanying drawing.