KR0145925B1 - Interrupt control apparatus of computer - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt control apparatus in the computer field suitable for enabling interrupt control having a multi-layered structure in multiple processors. In the related art, when the number of processors is further increased, the interrupt control of each processor is controlled using a single interrupt bus. Although it was difficult, in the present invention, a plurality of processor interrupts are efficiently performed by grouping a plurality of processors into groups so that each processor interrupt is performed in each group, and in some cases, processors in different groups perform interrupts. It is possible to improve the above drawbacks.

Description

Interrupt Control Device in Computer Field

1 is a block diagram illustrating an embodiment of a multiprocessor interrupt control device in the prior art computer field.

2 is a block diagram showing an embodiment of a multiprocessor interrupt control apparatus in the computer field according to the present invention.

3 is a detailed block diagram illustrating each processor unit in detail according to FIG. 2;

4 is a detailed block diagram illustrating each multiprocessor interrupt control unit according to FIG. 2 in more detail.

* Explanation of symbols for main parts of the drawings

12,14,16,22,24,26: 1st, 2nd, 3rd, 11th, 12th, 13th processor part

18,20: first and second multiprocessor interrupt

20,30: multiprocessor interrupt control

42 processor 44 local interrupt controller

52: Arbitration and Local Interrupt Interface Logic 54: Multi-Bus Interrupt Requester

56: Arbitration and Bus Interrupt Interface Logic 58: Multi-Bus Interrupt Handler

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to interrupt control in the computer field, and more particularly, to an interrupt control apparatus in the computer field suitable for enabling interrupt control having a multi-layered structure in multiple processors.

In this regard, FIG. 1 is a block diagram illustrating an embodiment of a multiprocessor interrupt control apparatus in the prior art computer field.

Such a multiprocessor interrupt control apparatus in the conventional computer field includes a local interrupt controller (4, 8) in each interrupt controller of processors 1, n (2, 6) each having an interrupt controller (Interrupt Controller). Are connected to each other, and each interrupt controller is connected to an interrupt bus.

Here, n is an arbitrary integer, which means that there are a plurality of processors.

In the prior art thus constructed, each processor 1, n (2, 6) communicates by requesting an interrupt from each other via an interrupt bus shared with each interrupt controller.

At this time, each of the local interrupt controllers 4 and 8 may request local interrupts to each of the processors 1, n (2, 6) through each interrupt controller by each local interrupt.

However, in this conventional technique, when the number of processors is further increased, it is difficult to control the interrupt of each processor using a single interrupt bus.

The present invention has been made to solve the drawbacks of the prior art, and the object of the present invention is to provide an interrupt control device in the computer field that can control the interrupt of each processor even if the number of processors in the computer field is further increased. have.

In order to achieve the above object, the present invention provides a first multiprocessor interrupt including a plurality of processor units which are respectively connected to a built-in local interrupt bus A, and each of which can perform an interrupt function with a counterpart processor unit therein. And a multiprocessor controlling an interrupt path between the first multiprocessor interrupt unit and the counterpart multiprocessor interrupt unit between the local interrupt bus A embedded in the first multiprocessor interrupt unit and the system interrupt bus. A second multiprocessor interrupt unit comprising a plurality of processor units each connected to an interrupt control unit, a built-in local interrupt bus B and capable of performing an interrupt function with a counterpart processor unit, respectively, and a second multiprocessor interrupt unit Internal Interrupt Bus B Characterized in that formed between the system interrupt bus that is shared with the relative multiprocessor interrupt control unit and a second multi-processor interrupt with the mating portion multiprocessor multiprocessor interrupt control unit for controlling the path of the interrupt and the interrupt section.

In this case, when the number of processor units is further increased, multiprocessors may be grouped into one or more groups according to the same principle as described above, so that the multiprocessor interrupt unit and the multiprocessor interrupt controller correspond one-to-one. One or more interrupt controllers may be formed.

Hereinafter, an embodiment of the present invention made as described above will be described in detail with reference to the accompanying drawings.

Referring to FIG. 2, FIG. 2 is a block diagram showing an embodiment of a multiprocessor interrupt control apparatus in the field of the computer according to the present invention, which is connected to a built-in local interrupt bus A and is interrupted with a counterpart processor unit therein. A first multiprocessor interrupt between the first multiprocessor interrupt unit 18, which includes a plurality of processor units capable of performing functions, and a local interrupt bus A and a system interrupt bus embedded in the first multiprocessor interrupt unit 18, respectively. It is connected to the multiprocessor interrupt control unit 20 for controlling the interrupt path between the unit 18 and the counterpart multiprocessor interrupt unit, and the built-in local interrupt bus B, respectively, to perform an interrupt function with the counterpart processor unit. A second multiprocessor interrupt unit 28 comprising a plurality of processor units; The second multiprocessor interrupt unit 28 and the first multiprocessor interrupt unit 18 between the local interrupt bus B built in the processor interrupt unit 28 and the system interrupt bus shared with the first multiprocessor interrupt control unit 18. It includes a multi-processor interrupt control unit 30 for controlling the interrupt path with the.

Here, the first, second and third processor units 12, 14, and 16 are formed in the first multiprocessor interrupt unit 18, and the 11, 12, and 12 units are formed in the second multiprocessor interrupt unit 28. The thirteenth processor unit 22, 24, and 26 are formed, and the first, second, third, eleventh, twelfth, and thirteenth processor units 12, 14, 16, 22, 24, and 26 are formed. If the number of multipliers increases further, the multiprocessor interrupt control unit may be grouped into one or more groups according to the above-described principles, thereby forming one or more multiprocessor interrupt control units so that the multiprocessor interrupt unit and the multiprocessor interrupt control unit correspond one-to-one. have.

The present invention thus made will be described with reference to FIGS. 3 and 4 as follows.

FIG. 3 is a detailed block diagram illustrating each processor unit 12, 14, 16, 22, 24, and 26 according to FIG.

4 is a detailed block diagram illustrating each of the multiprocessor interrupt controllers 20 and 30 according to FIG.

First, each of the processor units 12, 14, 16, 22, 24, and 26 of the first and second multiprocessor interrupt units 18 and 20 includes a processor 42 including an interrupt controller as well as a local interrupt. Consists of a controller 44, the local interrupt controller 44 communicates with the interrupt controller by a local interrupt to control the interrupt of the processor 42, and the processor 42 uses the local interrupt bus A or the local interrupt bus B. To perform the interrupt function with the other processor.

Next, each multiprocessor interrupt control unit 20 or 30 is connected to the local interrupt bus as shown in FIG. 4 to determine whether the interrupt belongs to the current multiprocessor interrupt unit or the other multiprocessor interrupt unit. Is different from Arbitration And Local Interrupt Interface Logic 52, which generates an interrupt request signal if the interrupt belongs to a part and takes control of the current local interrupt bus if an interrupt belonging to a current multiprocessor interrupt part. If the interrupt belongs to the multiprocessor interrupt unit, the interrupt request signal of the arbitration and local interrupt interface logic 52 is stored or the interrupt signal of the Multi BUS Interrupt Handler 58 is stored and the signal indicates that there is an interrupt. Receives a signal indicating that there is an interrupt of the multi-bus interrupt requester 54 and a multi-bus interrupt requester 54 generating a system, and seizes the system interrupt bus to receive the signal through the system interrupt bus. Arbitration And BUS Interrupt Interface Logic 56, which transmits to the multi-processor interrupt control section and outputs an interrupt signal from the system interrupt bus, and arbitration and bus interrupt interface logic depending on the interrupt source. A multi-bus interrupt handler 58 that stores the interrupt signal of 56 and informs the arbitration and local interrupt interface logic 52.

That is, the first multiprocessor interrupt unit 18 is composed of a plurality of processor units 12, 14, and 16 which are respectively connected to the embedded local interrupt bus A and which can each perform an interrupt function with each other. The multiprocessor interrupt control unit 20 may include the first multiprocessor interrupt unit 18 and the second multiprocessor interrupt unit 28 between the local interrupt bus A and the system interrupt bus embedded in the first multiprocessor interrupt unit 18. Control the interrupt path.

Next, the second multiprocessor interrupt unit 28 includes a plurality of processor units 22, 24, and 26 each connected to an internal local interrupt bus B, each of which may internally perform an interrupt function with a counterpart processor unit. The multiprocessor interrupt control unit 30 may include a second multiprocessor interrupt unit between a local interrupt bus B embedded in the second multiprocessor interrupt unit 28 and a system interrupt bus shared with the first multiprocessor interrupt control unit 18. An interrupt path between the 28 and the first multiprocessor interrupt unit 18 is controlled.

Also, as in the fourth case, the arbitration and local interrupt interface logic 52 is connected to the local interrupt bus to determine whether it is an interrupt belonging to one multiprocessor interrupt or an interrupt belonging to another multiprocessor interrupt. If the interrupt belongs to an interrupt request signal is generated, if the interrupt belongs to the current multiprocessor interrupt, the current local interrupt bus.

If the multi-bus interrupt requester 54 is an interrupt belonging to another multi-processor interrupt unit, the multi-bus interrupt requester 54 stores the interrupt request signal of the arbitration and local interrupt interface logic 52 or the multi-bus interrupt handler 58. The arbitration and bus interrupt interface logic 56 receives a signal indicating that there is an interrupt of the multi-bus interrupt requester 54 to take control of the system interrupt bus and transmit the signal through the system interrupt bus. Sends to the processor interrupt control section and outputs the interrupt signal from the system interrupt bus.

The multi-bus interrupt handler 58 then stores the interrupt signals of the arbitration and bus interrupt interface logic 56 in accordance with the interrupt source and informs the arbitration and local interrupt interface logic 52.

As described above, in the present invention, a plurality of processors are grouped into groups so that each processor interrupt is performed in each group, and in some cases, processors in different groups perform interrupts efficiently. It works.

Claims (2)

A first multiprocessor interrupt unit 18 comprising a plurality of processor units each connected to an internal local interrupt bus A and capable of performing an interrupt function with a counterpart processor unit internally. And a multiprocessor interrupt control unit controlling an interrupt path between the first multiprocessor interrupt unit 18 and the counterpart multiprocessor interrupt unit between the local interrupt bus A embedded in the first multiprocessor interrupt unit 18 and the system interrupt bus. 20; A second multiprocessor interrupt unit 28, each of which includes a plurality of processor units respectively connected to the embedded local interrupt bus B and capable of respectively performing an interrupt function with a counterpart processor unit; The second multiprocessor interrupt unit 28 and the multiprocessor interrupt unit 20 between a local interrupt bus B embedded in the second multiprocessor interrupt unit 28 and a system interrupt bus shared with the multiprocessor interrupt control unit 20. And a multiprocessor interrupt control unit (30) for controlling the interrupt path with the < RTI ID = 0.0 > 2. The method of claim 1, wherein at least one of the two multiprocessor interrupt controllers 20,30 is connected to a local interrupt bus to determine whether it is an interrupt belonging to a current multiprocessor interrupt or an interrupt belonging to another multiprocessor interrupt. Arbitration and local interrupt interface logic 52 to generate an interrupt request signal if it is an interrupt belonging to another multiprocessor interrupt and to take control of the current local interrupt bus if it is an interrupt belonging to the current multiprocessor interrupt; If the interrupt belongs to the other multiprocessor interrupt unit, the multi-bus for storing the interrupt request signal of the arbitration and local interrupt interface logic 52 or the interrupt of the multi-bus interrupt handler 58 and generating a signal indicating the interrupt is present. An interrupt requester 54; Receives a signal indicating that there is an interrupt of the multi-bus interrupt requester 54, takes control of the system interrupt bus, transmits it to the multi-processor interrupt control unit through the system interrupt bus, and receives an interrupt signal from the system interrupt bus. An arbitration and bus interrupt interface logic 56 for outputting; And a multi-bus interrupt handler (58) for storing interrupt signals of the arbitration and bus interrupt interface logic (56) according to the interrupt source and informing the arbitration and local interrupt interface logic (52).