JP2810112B2 - Interrupt control method and device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system, and more particularly to an interrupt control method and apparatus for a system in which a plurality of interrupts enter the same level.

[Conventional technology]

In a conventional computer system, in a system configuration in which multiple interrupts enter the same interrupt level for a central processing unit, when an interrupt to the central processing unit occurs, the central processing unit is registered in advance at system startup. In general, there is a method of sequentially examining all interrupt generating devices which may generate an interrupt to the same level and specifying an interrupt generator.

[Problems to be solved by the invention]

The prior art described above is based on the problem that, when there are a large number of interrupt generators that generate an interrupt at the same interrupt level, when an interrupt occurs at the interrupt level, the central processing unit performs the interrupt from the occurrence of the interrupt. No consideration was given to the fact that the time required to identify the interrupt generating device that generated the interrupt was long, and in a system that required a high-speed response, the processing speed did not satisfy the request. .

Further, in the above-described conventional technology, when registering an interrupt generation device that generates an interrupt to the same interrupt level with respect to the central processing unit at system startup, a registration error or registration omission may occur. There was a problem that the central processing unit could not respond to an interrupt from an unregistered interrupt generating device, and the system was shut down.

An object of the present invention is to provide a system in which a plurality of interrupt generators that generate an interrupt to the same interrupt level have a high speed when the central processing unit generates an interrupt to the central processing unit. An object of the present invention is to provide an interrupt control method and an apparatus that can determine an interrupt generation device.

Another object of the present invention is to eliminate the need for registering an interrupt generator that generates an interrupt to the same interrupt level with the central processing unit when the system is started up, and to be able to flexibly cope with additions and changes of the system. An object of the present invention is to provide an interrupt control method and apparatus.

[Means for solving the problem]

In order to achieve the above object, when an interrupt occurs, the central processing unit reads a specific address to request each interrupt generator to report the presence or absence of an interrupt and a request for a report of the presence or absence of the interrupt. The interrupt generating device which generated the interrupt by providing an interrupt generating report circuit and a signal line, and connecting the interrupt generating report signal line of each interrupt generating device to a different data line of the central processing unit. Things.

In order to achieve the above and other objects, the central processing unit and the interrupt generation device are configured by a card, and the central processing unit and the interrupt generation device are connected by a backboard and a connector, and the interruption generation of the interrupt generation device is performed. The interrupt generation device outputs a report signal to the same terminal number of the connector, and the interrupt generation report signal assigned to the same terminal number of each connector is connected to the central processing unit and the corresponding interrupt signal for each connector on a backboard. Are connected on different data lines connecting the intrusion generators.

[Action]

The interrupt occurrence presence / absence report request circuit transmits an interrupt occurrence presence / absence report request signal to the interrupt generation device when the central processing unit accesses a specific address. The interrupt generation device that has generated the interrupt among the interrupt generation devices that have received the interrupt generation presence / absence report request signal activates the interrupt generation report signal. The interrupt generation report signal is connected to a different data line for each of the interrupt generation devices, and since the data line is connected to the central processing unit, the central processing unit reads data on the data line. Thus, it is possible to determine which interrupt generating device has generated the interrupt. For this reason, the central processing unit accesses the specific address only once after the occurrence of the interrupt, and can correctly determine the source of the interrupt only by reading the data.

Further, in the present invention, when all the interrupt generation devices included in the system generate an interrupt, the interrupt generation report is performed to the central processing unit by the interrupt generation presence / absence report request signal from the central processing unit, An interrupt generator not included in the system cannot generate an interrupt to the central processing unit. In this way, when the system is started up, the central processing unit does not need to register the interrupt generating device with the central processing unit, and when the interrupt occurs, the central processing unit can determine the interrupt generating device that generated the interrupt. No system down.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of one embodiment of the present invention. The central processing unit 1 includes an MPU (Main Processing Unit) 11, a MEM (MEMory) 12 for storing programs and data, an identification signal requesting circuit 13, a data input buffer 14, and an internal bus 15 connecting these. The central processing unit 1 and the interrupt generators (INT1 to INT16) 2 are connected by an interrupt line 4, an interrupt generator identification signal output timing line 5, and a data bus 3.

The reason why the interrupt generators (INT1 to 16) 2 are connected to the central processing unit 1 by one interrupt line 4 is that the interrupt generators (IN
T1-16) 2 is to generate an interrupt of the same level to the central processing unit 1.

The timing at which the INTs 1 to 16 generate an interrupt is random, and a plurality of interrupts may occur at the same time.

FIG. 2 shows the processing of the MPU 11 when an interrupt is received from the interrupt generator (INT1 to 16) 2 via the interrupt line 4 to the MPU 11 of FIG.

 Hereinafter, the processing when an interrupt occurs will be described with reference to FIG.

When the MPU 11 recognizes the occurrence of the interrupt through the interrupt line 4, the MPU 11
Reads the interrupt generator identification I / O address (111). In this process, a timing signal is output from the identification signal request circuit 13 in FIG. 1 to the interrupt generator identification signal output timing line 5. An interrupt generation signal that generates an interrupt among the INT1 to INT16 by the timing signal outputs an identification signal to the data bus 3. The identification signal is taken into the data input buffer 14.

Next, the MPU 11 secures an interrupt generator based on the data taken into the data input buffer 14 (112).

If the interrupt generators are INT2 and INT16 in FIG. 1, the data that the MPU 11 takes in the data input buffer 14 is as shown in FIG. MPU11 from this
Can determine that the interrupt generators are INT2 and INT16.

Finally, the MPU 11 performs processing for the determined interrupt generator (113).

According to the present embodiment, in a system in which 16 interrupts occur at the same level, the time from the occurrence of an interrupt until the determination of the interrupt generator is determined by one I / O read. Can be determined, and can be reduced to about 1/16 compared to the conventional polling method.

Also, according to the present embodiment, the interrupt generation device connected to the system of the present embodiment sends an identification signal to the central processing unit when an interrupt occurs, so that the central processing unit Since the connection to the system can be recognized, when INT1 is removed in FIG. 1, it is not necessary to register the system configuration change in the central processing unit when the system configuration is changed. Therefore, there is an effect that the system configuration can be changed only by physically connecting or disconnecting the device.

FIG. 4 shows an embodiment of an implementation device for realizing the present invention.

It has the functions of the central processing unit 1 of FIG. CPU (Cen
The tral processing unit (card) 10 and the interrupt generation card 20 are connected to the back boat 7 by the connector 6.

The shapes of the connectors 6 are all the same, and the card can be connected to any connector.

 FIG. 5 is a detailed block diagram of FIG.

As shown in the figure, the backboard 7 is connected to the data bus 3
0, an interrupt line 40, and an interrupt generator identification signal output timing line 50 are provided. Further, the interrupt line 40 and the interrupt generator identification signal output timing line 50 are connected to the connector to which the interrupt generating card is connected.
Connect them to the same terminals of CN1 to CN16 respectively, and connect the interrupt generator identification signal receiving terminals (hatched parts in Fig. 5) assigned to the same terminal numbers of connectors CN1 to CN16 to D0 to D15 of data bus 30, respectively. doing.

According to the present embodiment, when an interrupt occurs, the CPU card 10 can recognize to which connector the interrupt occurrence card 20 is mounted by the interrupt person identification signal, There is an effect that an arbitrary system can be constructed only by connecting an arbitrary number of connectors to an arbitrary connector. Furthermore, since system configuration registration is not required for the CPU card when constructing the system, there is an effect that a system down due to a system configuration registration error or a human error such as system configuration registration omission can be prevented.

In the above-described embodiment, the number of interrupt generators, the number of data buses, and the number of connectors are set to 16, but the present invention is not limited to these, and the numbers are arbitrary.

FIG. 6 is a configuration diagram of an embodiment of an application system equipped with the present invention.

CPU 100, process input device 201, process output device 202,
A controller 8 including a process input / output device 203 and a system bus 70 is a control controller that controls outputs such as valve opening / closing amounts 92 and 94 based on inputs from sensors 91 and 93 attached to the process 9 to be controlled. It is.

CPU 100, process input device 201, process output device 202, process input / output device 203 included in the controller 8
Have the card shapes shown in FIG.
Has the functions of the central processing unit 1 of FIG. 1, and includes a process input device 201, a process output device 202, and a process input / output device 20.
3 has the function of the first interrupt generation device 2. Further, the system bus 70 includes a data bus 3, an interrupt line 4, and an interrupt generator identification signal output timing line 5 shown in FIG.
As shown in FIG. 4, it has a backboard configuration.

According to the present embodiment, from the time when any of the process input device 201, the process output device 202, or the process input / output device 203 (simultaneously, a plurality of processes is allowed) occurs until the CPU 100 determines the interrupt occurrence card. Can be reduced to 1 / card number compared to the conventional polling method.

Further, according to the present embodiment, when an interrupt occurs, the CPU 100 is mounted with the process input device 201, the process output device 202, and the process input / output device 203 in any connector by the interrupt generator identification signal. Process input device 201, process output device 202,
The system configuration can be changed only by mounting an arbitrary number of process input / output devices 203 in an arbitrary combination. Furthermore, since the system configuration registration is not required for the CPU 100 when the system configuration is changed, it is possible to prevent the operation of the control target process from being stopped due to a system configuration registration error or a human error such as a system configuration registration omission. effective.

Further, by configuring the controller 8 with one back board, a compact controller can be realized.

In the above embodiment, the CPU 100, the process input device 201,
Although the realization of the process output device 202 and the process input / output device 203 is a card configuration, and the realization of the system bus 70 is a backboard, the present invention is not limited thereto.

〔The invention's effect〕

According to the present invention, when an interrupt to the central processing unit occurs,
The central processing unit accesses the specific address only once and reads the data to determine which interrupt generating device is the source of the interrupt, so that a plurality of interrupts enter the same level. In the system, even when the number of interrupt generation devices increases, the processing speed does not decrease. That is, there is an effect that high-speed processing can be realized regardless of the number of interrupt generation devices.

Further, according to the present invention, at the time of system startup, not only the effect that registration of the interrupt generation device with respect to the central processing unit becomes unnecessary, but also registration error of the interrupt generation device and registration omission do not occur. Therefore, when an interrupt occurs, there is a great effect that the possibility of system down occurring due to the central processing unit being unable to determine the interrupt generating device that caused the interrupt can be reduced to zero.

Further, according to the present invention, the interrupt generation report signals allocated to the same terminal of each connector are connected to different data lines for each connector on the backboard, so that the interrupt generation devices having the same structure can be combined in any combination. There is an effect that a system can be constructed only by connecting to an arbitrary connector.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
MPU processing flowchart when an interrupt is input to the MPU, FIG. 3 is a diagram showing an example of data taken by the MPU, FIG. 4 is a diagram showing an embodiment of an implementation device for realizing the present invention, FIG. 5 is a detailed block diagram of FIG. 4, and FIG. 6 is a block diagram of an embodiment of an application system equipped with the present invention. DESCRIPTION OF SYMBOLS 1 ... Central processing unit, 2 ... Interrupt generator, 3 ... Data bus, 4 ... Interrupt line, 5 ... Interrupt generator identification signal output timing line, 6 ... Connector, 7 ... Backboard .

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Mitsuro Takakura 5-2-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside the Hitachi, Ltd. Omika Plant (56) References JP-A-51-96259 (JP, A) JP-A-57-14931 (JP, A) JP-A-60-221859 (JP, A) JP-A-57-159320 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 9 / 46 G06F 15/16 G06F 13/10-13/14 G06F 13/20-13/42 G06F 1/18 G06F 3/00 G05B 19/05

Claims (1)

(57) [Claims] 1. An interrupt control device for a system including a central processing unit and a plurality of interrupt generation devices connected to a backboard for generating an interrupt of the same level to the central processing unit, The processing device is connected to an identification signal request circuit that detects a read access to a specific address by the MPU of the central processing unit and issues an identification signal output request to each interrupt generation device, and is connected to an internal bus of the central processing device. A data bus comprising a plurality of data lines, and a system bus having an interrupt line for notifying the MPU of occurrence of an interrupt from each interrupt generation device and an identification signal output request line. And a plurality of connectors connected to the system bus, wherein the interrupt line and the identification signal output request line are connected to a terminal number common to the connectors, An identification signal receiving end assigned to a common terminal number in the connector is connected to one of the data lines different from each other for each connector, and each interrupt generating device connected to the backboard by the connector is When an interrupt is generated from the interrupt generation device, an interrupt signal is output to a terminal to which the interrupt line is connected, and the request for the identification signal is transmitted to the identification signal receiving end assigned to the same terminal number of the connector. An interrupt generation device; and a circuit for outputting an identification signal of the interrupt generation device, wherein the data input buffer fetches the identification signal from each data line of the data bus and outputs the identification signal to the data line of the internal bus. apparatus.