KR920000480B1 - Arbitration method of interrupt bus - Google Patents

Abstract

The method is to support interprocess communication of multiprocessor system. When an interrupt request signal is received, arbiters are drived fromthe first bit according to thepriorities to allow the usage of interrupt bus for processors. The circuit includes an interrupt requester (5) for request arbitration to interrupt handlers (3,4) when the interrupt request signal from processors (1,2) is received, interrupt handlers (3,4) for processing the arbitration request and interrupts occured in boards in which processors are deposited, an interrupt arbiter (7) for executing the arbitration and sending the result to the interrupt requestor (5), and for arbitrating the interrupt handlers, and an interrupt bus synchronizing signal (IBSYNC) driver (8) for generating the IBSYNC signal to drive the signal line (9) and for sending the IBSYNC signal to the interrupt requester (5).

Description

How to Arbitrate Interrupt Buses

1 is a block diagram showing the configuration of the present invention.

2A is a block diagram showing the configuration of the interrupt arbiter of the present invention.

(b) is a circuit diagram of a 1-bit arbiter of the present invention.

The present invention relates to a method of arbitrating an interrupt bus for supporting interprocess communication in a multiprocessor system in which several processors share multiple memories.

In the conventional uniprocessor system, an interrupt transmission method allocates signals to a type of interrupt or a module that can request an interrupt, and the central processor processes interrupts according to each signal and the state of the processor. I did. However, in a multiprocessor system in which several processors share multiple memories, there are many processors capable of handling interrupts and the number of modules capable of interrupting is greatly increased, which is the same as in a conventional single processor system. When the interrupt is transmitted by the method, a large number of signals are required, which leads to a complicated transmission of the interrupt and a lot of errors during the transmission.

Accordingly, an object of the present invention is to provide a method of arbitrating an interrupt bus for supporting communication between processors in a multiprocessor system. To this end, in the multiprocessor system in which only one interrupt is given to the processor and there are several processors operating with equal qualifications, the interrupt bus assigns an interrupt to each processor and sends an interrupt to all processors simultaneously. As well as selecting a processor to handle the interrupt, as well as select one of a plurality of processors requesting the interrupt to facilitate the transmission of the interrupt.

The present invention will be described in detail with reference to the accompanying drawings as follows.

1 is a block diagram of an exemplary embodiment of the present invention. In a multiprocessor system in which two processors are paired in a state in which multiple processors share multiple memories, an interrupt request from the processors 1 and 2 is received. Interrupt Requester (5) which receives the mediation request to the interrupt handlers (3) and (4), and the board to which the arbitration requested by the interrupt requester (5) and the processors (1) and (2) belong. Interrupt handler (3), (4) and interrupt requester (5) for informing the corresponding processors (1) and (2) while processing the interrupt generated in the bus through the interrupt bus (6). Interrupt Arbiter 7 and the Interrupt Bus Synchronization Signal which perform an arbitration process and transmit the result to the interrupt requester 5 or perform an arbitration process between the interrupt handlers 3 and 4. Interrupt Request (IBSYNC) Driving the interrupt synchronizing signal IBYNC, which is generated by the control of the instrument 5 and is driven to the signal line 9 or transmitted to the interrupt bus requester 5 by the interrupt bus synchronizing signal IBSYNC transmitted through the signal line 9; A receiver 8 and a clock generator 10 for generating an interrupt bus clock signal IBYNC and driving the signal line 11 are provided.

FIG. 2A shows the configuration of the interrupt arbiter 7, in which arbitration information Arbitration is input from the interrupt bus requester 5 to the input terminal I, respectively, 12 bit 12, 12a, 12b. ) ... (12n) is connected so that a request signal is input to the input terminal (req) of the first 1-bit arbiter 12, and the arbitration information (Arbitration) at the output terminal (A) is an interrupt handler. In the output stage W, the arbitration success signal WIN is output to the input terminal req of the second 1-bit arbiter 12a while outputting to one of (3) and (4). Arbitration success signal (WIN) at the output terminal (W) of to inform the interrupt requester (5) whether the mediation success.

FIG. 2b is a circuit diagram of a 1-bit arbiter. Arbitration of the interrupt requester 5 is applied to one side of two NAND gates N1 and N2 directly or via an inverter I1. The request signal is applied to one side of the NAND gate N1 and the AND gate A, and the arbitration information output from the NAND gate N1 to the interrupt handlers 3 and 4 is converted to the inverter (N). Arbitration success signal WIN is output from the output terminal of the AND gate A by being input to the other side of the NAND gate N2 through I2) and applied to the other side of the AND gate A at the output terminal of the NAND gate N2. To make it appear.

Therefore, if there are many interrupt requesters who want to send interrupts at the same time, the arbitration cycle to handle them without conflict is started only when there is an interrupt request by the interrupt requester. The sync signal IBSYNC is driven ″ false ″ to indicate that the next period of the interrupt bus clock signal IBCLK may be an arbitration period. In the arbitration method, an interrupt arbiter with a large number of 1-bit arbiters representing high to low digits (usually about 8 digits) is selected from the first 1-bit arbiter to the next by the interrupt requester according to the priority set by the processor. The corresponding 1-bit arbiter will be driven either ″ high ″ or ″ Low ″ in turn. At this time, if two or more modules simultaneously drive the signal to the interrupt bus, only the ″ Low ″ value is displayed and the signal sent from the module is selected. Therefore, when the signal appears as the ″ Low ″ value, the next drive stops. There is only one interrupt arbiter that has finished driving up to 1-bit arbiter, so only one interrupt requester is selected.

Claims (3)

In a multiprocessor system in which several processors share multiple memories, the interrupt requester 5 receiving the interrupt bus sync signal IBSYNC through the interrupt sync drive and the receiver 8, and the interrupt requester 5, It consists of an interrupt arbiter (7) which selects one of two interrupt handlers (3) and (4) by an interrupt request, and starts from the higher bit 1 bit arbiter in order to determine the priority when there is an interrupt request. A method of arbitration of an interrupt bus which allows the arbitration for the interrupt bus to be performed while arbitration is performed for the use of the interrupt bus (6). 2. The interrupt arbiter 7 receives arbitration information and a request signal, and outputs the arbitration information to the interrupt handlers 3 and 4 through the NAND gate N1. A method of arbitration of an interrupt bus which is output as an arbitration success signal (WIN) to an input terminal (req) of the next 1-bit arbiter via an inverter (I1) (I2), a NAND gate (N2), and an AND gate (A). The method of claim 1, wherein the arbitration success signal WIN of the last 1-bit arbiter 12n of the interrupt arbiter 7 is inputted to the interrupt requester 5 to drive the last 1-bit arbiter 12n. The method of arbitration of the interrupt bus to indicate that the arbitration was successful.

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