KR950013843B1 - Arbiration method and unit of multiplexing bus - Google Patents

Abstract

The multiplexing bus arbitrating method comprises the steps of: converting bus request signals transmitted to a plurality of bus controllers into active signals; selecting one of the active signals by checking bus permission signals received from the bus controllers and maintaining the selected signal as an active signal and converting the remaining signals into nonactive signals; converting the state of the bus permission perceiving signal transmitted to a designated bus controller according to the bus permission signal into an active state and then receiving/transmitting various data by using the bus; and generating a bus return signal after the reception/transmission of the data.

Description

Multiplexed bus arbitration method and apparatus

1 is a diagram showing the structure of a general multiplexed bus.

2 shows an example of a conventional bus allocation map.

FIG. 3 is a waveform diagram illustrating general ablation signals.

4 is a diagram showing the structure of a multiplexed bus to which the present invention is applied.

5 is a flowchart showing a multiplexed bus arbitration method according to the present invention.

6 is a block diagram showing a multiplexed bus arbitration apparatus according to the present invention.

7 is a detailed block diagram according to an embodiment of the present invention, the multiplexed bus arbitration apparatus.

8 is a waveform diagram of each part of the multiplexed bus arbitration apparatus shown in FIG.

* Explanation of symbols for main parts of the drawings

PE1, PE2,... PEn: Multiple processors ME1,... , MEm: multiple memories

I / Ol,… I / Ok: Multiple output terminals 601: Bus selection means

602: bus permission acknowledgment signal generating means 603: multiple bus request signal generating means

The present invention relates to a multiplexed bus arbitration method and apparatus for performing bus control, and more particularly, to a method and apparatus performed in a bus arbiter attached to each processor of a multiprocessor system using a multiplexed bus.

FIG. 1 is a diagram illustrating a structure of a general redundant bus. The A bus controller 101, the B bus controller 102, a plurality of processors PE1, PE2,..., PEn, and a plurality of memories ME1,. MEm) and a plurality of input / output terminals (I / Ol,… I / Ok) are commonly connected to the two buses (A bus and B bus), and each bus is a data bus to which data is transmitted and an address to which an address is transmitted. It consists of a bus and a control bus through which various control signals are transmitted. The A bus controller 101 and the B bus controller 102 perform a function of selecting one of a plurality of processors that send a bus request signal to use the corresponding bus and allocating the bus to it. A more detailed description thereof will be made with reference to FIG. 3.

In FIG. 1, each of the processors PE1, PE2,..., And PEn includes a multiplexing bus arbitration device (arbiter) for managing an interface with each bus connected thereto although not shown in the drawing.

A conventional multiplexing bus arbitration apparatus will now be described with reference to FIGS. 2 and 3.

2 illustrates an example of a conventional bus allocation map, in which each of the processors PE1, PE2,..., And PEn has each of the memories ME1,..., MEm and the input / output terminals I / Ol,... / Ok) is a predefined bus to use for access. For example, the processor PE3 must use bus B to access the memory ME2, and the bus A must be used to access the input / output terminal I / Ol. Therefore, the conventional multiplexed bus arbitration apparatus only performed the interface with the designated bus.

3 is a waveform diagram of signals transmitted and received to perform an interface with a designated bus, and includes a bus clock signal (/ BLOCK), a bus request signal (/ BR), a bus permission signal (/ BG), and a bus permission recognition. The signal / BGACK is shown.

In FIG. 3, the bus clock signal / BLOCK is a synchronous clock of signals transmitted and received on the bus, and the bus request signal / BR is a signal transmitted from the multiplexed bus arbitration apparatus to the bus controller according to the request of the processor. The bus controller receives such a bus request signal (/ BR) from a plurality of processors, selects one of the processors according to a predetermined algorithm, and then sends the bus permission signal (/ BG) to the multiplexed bus arbitration apparatus of the selected processor. Will be sent. The multiplexing bus arbitration apparatus receiving the bus permission signal / BG transmits a bus permission acknowledgment signal / BGACK indicating that the bus permission signal / BG has been received to the corresponding bus controller. When the bus permission signal / BG is transmitted, data, address and control signals are transmitted by using the bus while the bus permission signal / BG is active. In FIG. 3, ① indicates a point at which a bus request is made, ② indicates a period during which the processor uses the bus, and ③ indicates a point where the bus is returned.

However, the conventional multiplexing bus arbitration apparatus as described above has a problem in that the utilization rate of the bus is lowered because only a designated bus is used even though a plurality of buses are substantially connected, thereby reducing the efficiency of the system. In other words, if a processor (PEi) is specified to use the bus when accessing some memory (MEj), there is a problem of waiting for bus A to become available even if bus B is available. Will occur.

Accordingly, an object of the present invention is to provide a multiplexed bus arbitration method that can solve the above problems and increase the utilization of the bus.

Another object of the present invention is to provide a multiplexing bus arbitration apparatus for performing an interface with a plurality of buses by generating an ablation signal according to the multiplexing bus arbitration method.

In order to achieve the above object, in the multiplexed bus arbitration method of the present invention, a plurality of buses are connected to each processor through a multiplexed bus arbitration apparatus, and a bus is controlled by each processor of a multiprocessor system including a bus controller for each bus. A method for converting a bus request signal transmitted to a plurality of bus controllers into an active method, the method comprising: converting a bus request signal into an active state; Examining bus permission signals received from the plurality of bus controllers, selecting one of the active signals, preserving it as active, and converting the remaining signals into non-active; Converting a state of a bus permission acknowledgment signal transmitted to a bus controller designated according to an optionally activated bus permission signal to an active state and causing a processor to transmit and receive various data using the bus; After the transmission and reception of data is characterized in that it comprises a process for generating a signal returning the bus.

In order to achieve the above object, the multiplexing bus arbitration apparatus of the present invention has a plurality of buses connected to each processor, and includes a bus controller for each bus, wherein all bus permits are received from the bus controller. Multiple bus request signal generating means for generating a plurality of bus request signals that are activated when the recognition signals are non-active and the signal / Pbr indicating a bus use request from the processor is active; Bus selecting means for selecting one of the bus permission signals that are received from the plurality of controllers and keeping the signal active and storing the other bus permission signals non-active; And a bus permission acknowledgment signal generating means for activating and outputting only a bus permission acknowledgment signal transmitted to a bus controller that is selectively designated according to an activated bus permission signal.

Thus, the present invention will be described in more detail with reference to FIGS. 4 to 8.

4 is a diagram illustrating a structure of a multiplexed bus to which the present invention is applied. A plurality of buses are connected to a processor through a multiplexed bus arbitration apparatus, and buses are connected to bus controllers for controlling bus use.

FIG. 5 is a flowchart illustrating a method of generating an arbitration signal, that is, a multiplexed bus arbitration method, transmitted and received in a bus control period when multiple buses are connected to a single processor through a multiplexed bus arbitration device as shown in FIG.

5, in step 501, the bus request signal / BR transmitted from the multiplexed bus arbitration apparatus to the plurality of bus controllers is switched to active. When such a bus request signal / BR is transmitted to a plurality of bus controllers, the multiplexed bus arbitration apparatus may determine the state of the bus permission signals / BG_A, / BG_B, ... received from the respective bus controllers in step 502. After the check is detected to be active, one of the active bus permission signals is selected. Here, when only one bus permission signal is activated, the bus permission signal is selected. When a plurality of bus permission signals are activated, one bus permission signal is selected according to a predetermined rule. Step 503 is a step of performing a branch operation according to the selected bus permission signal.

Steps 504 to 506 are performed when the A bus permission signal / BG_A is selected. In operation 504, the multiplexing bus arbitration apparatus switches the bus permission acknowledgment signal / BGACK transmitted to the A bus controller 101 to an active state. Since the right to use the A bus is performed, the data is transmitted and received using the A bus in step 505. When the transmission and reception of data is finished, the multiplexing bus arbitration apparatus generates a signal for returning the bus in step 506.

Steps 507 to 509 are performed when the B bus permission signal / BG_B is selected. After the bus permission acknowledgment signal / BGACK for the B bus is switched to active in step 507, the B bus permission signal / BG_B is selected. In step 508, data is transmitted and received using the B bus, and in step 509, the B bus is returned. That is, the steps 507 to 509 may be regarded as the same as the steps 504 to 506 as long as the signals for the A bus are replaced with the signals for the B bus. Although not shown in the drawing, when the system is configured to make more buses available to one process, the algorithms of steps 504 to 506 may be converted to those for the corresponding bus and further illustrated.

6 is a block diagram showing a multiplexed bus arbitration apparatus capable of performing operations according to the algorithm described in FIG. 5, wherein the bus selecting means 601, the bus permission acknowledgment signal generating means 602, and the multiple bus request signal generating means. 603 is configured.

In FIG. 6, the multiple bus request signal generating means 603 inputs a bus use request signal / Pbr indicating a bus use request from the processor and outputs a plurality of bus permission outputs from the bus permission recognition signal generating means 602. Input the acknowledgment signals / BGACK_A, BGACK_B, ... to the respective bus controllers when all bus permission acknowledgment signals / BGACK_A, BGACK_B, ... The bus request signals / BR_A, BR_B, ... transmitted are made active and output.

The bus selecting means 601 inputs the bus request signals / BR_A, BR_B, ... that are transmitted and received from the plurality of controllers, and then selects only one of the active signals and keeps them in an active state. By converting to an active state and outputting, it is possible to perform a function of selecting one of a plurality of licensed buses.

The bus permission acknowledgment signal generating means 602 inputs the signals / Pbr and the output signals of the bus selecting means 601 to provide a bus permission for the selected bus among the bus permission acknowledgment signals / BGACK_A, BGACK_B,... Only active signals are outputted.

7 shows a detailed block diagram according to an embodiment of the multiplexing bus arbitration apparatus of the present invention, wherein the bus selecting means 601 includes two inverters I1 and I2, two logical sum means OR1 and OR2, and two The multi-bus request signal generating means 603 is configured to include delay units D-FF1 and D-FF2, and includes two logical sum means OR3 and OR4, and the bus permission acknowledgment signal generating means 602. ) Includes a logical product inverting means (ND) and a logical sum means (OR5). In particular, Fig. 7 is configured to operate in the "0" level active as the normal multiplexed bus arbitration apparatus and the bus controller are configured with the negative logic "0" level active.

In FIG. 7, the first logical sum means PR1, the second logical sum means OR2, the first inverter I1, and the second inverter I2 perform input / output functions as shown in Table 1 below.

TABLE 1

As can be seen from Table-1, it can be seen that the values of the outputs X2 and X2 do not become active, that is, "0" at the same time. The output signals X2 and Y2 are applied to two delayers D-FF1 and D-FF2. The delay units D-FF1 and D-FF2 latch the signal input in the "1" level section of the bus clock signal / BLOCK and output the signal at the falling edge. The output signals X2 and Y2 are output. Delays to the next falling edge of the bus clock signal (/ BLOCK). The delayed signals X1 and Y1 are applied to the third logical sum means OR3 and the fourth logical sum means OR4 and are respectively ORed with the signal / Pbr. That is, the third logical sum means OR3 and the fourth logical sum means OR4 are signals that are activated when the signal / Pbr applied from the processor is active and the output of the corresponding bus among the outputs of the bus selection means 601 is active. Le will occur.

On the other hand, the logical product inverting means ND performs a function of performing an AND operation on the output signals X1 and Y1 of the bus selecting means 601 and then inverting them. Will print. The output of the logical product inversion means that the bus is allocated to the processor, and the bus request signal is not duplicated. In order to perform this function, the fifth logical sum means OR5 outputs a signal that is activated when the output of the logical product inversion means ND is non-active and the signal / Pbr indicating a bus request from the processor is active. Transfer to bus controller.

8 is a waveform diagram of each part of the multiplexed bus arbitration apparatus shown in FIG. 7, where ① indicates a point at which a bus request is made, ② indicates a period during which the processor uses the bus, and ③ indicates a point at which the bus is returned. Indicates. As can be seen from the figure, when data transmission and reception are finished, the signal (/ Pbr) indicating the bus use request is first converted into non-active by the processor, and thus the A bus permission acknowledgment signal (/ BGACK_A) is converted into non-active. It is returned by bus.

As described above, the present invention relates to a multiplexing bus arbitration method and apparatus for efficiently using the multiplexing bus, and has an effect of improving the overall performance of the system.

Claims (6)

In the method for controlling a bus in each processor of a multi-processor system, in which a plurality of buses are connected to each processor through a multiplexed bus arbitration device and including a bus controller for each bus, the bus request is transmitted to a plurality of bus controllers. Converting the signals into active; Inspecting bus permission signals received from the plurality of bus controllers, selecting one of the active signals, keeping the signal active, and converting the remaining signals into non-active; Converting a state of a bus permission acknowledgment signal transmitted to a bus controller designated according to an optionally activated bus permission signal to an active state and causing a processor to transmit and receive various data using the bus; And generating a signal for returning the bus when data transmission and reception is finished. In a multiprocessor system, in which a plurality of buses are connected to each processor and include a bus controller for each bus, all bus permission acknowledgment signals received from the bus controller are non-active and signals indicating a bus usage request from the processor. Multiple bus request signal generating means for generating a plurality of bus request signals that are activated when (/ Pbr) is active; Bus selecting means for selecting one of the bus permission signals that are received from the plurality of controllers and keeping the signal active and storing the other bus permission signals non-active; And bus permission acknowledgment signal generating means for activating and outputting only a bus permission acknowledgment signal transmitted to a bus controller which is selectively designated according to an activated bus permission signal. 3. The apparatus of claim 2, wherein the bus selecting means comprises: first logical sum means for ORing the first bus permission signal and the other signal when there are two buses available to the processor and operating at " 0 " level active; First inverting means for inverting the output of the first logical sum means; Second logical sum means for ORing the second bus permission signal and the output of the first inverting means; And a second inverting means for inverting the output of the second logical sum means and applying it to the other input of the first logical sum means. 4. The apparatus of claim 3, wherein the bus selecting means comprises: a first delay unit for delaying the output of the first logical sum means to an edge of a bus clock signal; And a second delayer for delaying the output of said second logical sum means to the edge of a bus clock signal. 3. The signal according to claim 2, wherein the bus permission acknowledgment means is input from the processor and indicates a bus usage request when there are two buses available to the processor and operate at " 0 " level active. Third logical sum means for ORing the first bus permission signal converted by the bus selecting means; And a fourth logical sum means for ORing a signal (/ Pbr) input from the processor to indicate a bus use request and the second bus permission signal converted through the bus selecting means. 3. The multi-bus request signal generating means according to claim 2, wherein the multi-bus request signal generating means performs an AND logic operation on the inverses of the outputs of the bus selecting means when there are two buses available to the processor and operate at " 0 " level active. ; And a fifth logical sum means for logically combining a signal (/ Pbr) input from the processor and a request for bus usage and the output of the logical product inverting means.